]> git.sur5r.net Git - u-boot/blobdiff - drivers/mmc/rockchip_sdhci.c
Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR
[u-boot] / drivers / mmc / rockchip_sdhci.c
index 624029bd20a3a94ff9ea7a958ad0f54680ef955b..8868f341f3375f0bb40e220b9b914030120fd153 100644 (file)
@@ -8,15 +8,20 @@
 
 #include <common.h>
 #include <dm.h>
-#include <fdtdec.h>
-#include <libfdt.h>
+#include <dt-structs.h>
+#include <linux/libfdt.h>
 #include <malloc.h>
+#include <mapmem.h>
 #include <sdhci.h>
+#include <clk.h>
 
 /* 400KHz is max freq for card ID etc. Use that as min */
 #define EMMC_MIN_FREQ  400000
 
 struct rockchip_sdhc_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+       struct dtd_rockchip_rk3399_sdhci_5_1 dtplat;
+#endif
        struct mmc_config cfg;
        struct mmc mmc;
 };
@@ -32,12 +37,39 @@ static int arasan_sdhci_probe(struct udevice *dev)
        struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
        struct rockchip_sdhc *prv = dev_get_priv(dev);
        struct sdhci_host *host = &prv->host;
-       int ret;
+       int max_frequency, ret;
+       struct clk clk;
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+       struct dtd_rockchip_rk3399_sdhci_5_1 *dtplat = &plat->dtplat;
+
+       host->name = dev->name;
+       host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
+       max_frequency = dtplat->max_frequency;
+       ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &clk);
+#else
+       max_frequency = dev_read_u32_default(dev, "max-frequency", 0);
+       ret = clk_get_by_index(dev, 0, &clk);
+#endif
+       if (!ret) {
+               ret = clk_set_rate(&clk, max_frequency);
+               if (IS_ERR_VALUE(ret))
+                       printf("%s clk set rate fail!\n", __func__);
+       } else {
+               printf("%s fail to get clk\n", __func__);
+       }
 
        host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
+       host->max_clk = max_frequency;
+       /*
+        * The sdhci-driver only supports 4bit and 8bit, as sdhci_setup_cfg
+        * doesn't allow us to clear MMC_MODE_4BIT.  Consequently, we don't
+        * check for other bus-width values.
+        */
+       if (host->bus_width == 8)
+               host->host_caps |= MMC_MODE_8BIT;
 
-       ret = sdhci_setup_cfg(&plat->cfg, host, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ,
-                       EMMC_MIN_FREQ);
+       ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ);
 
        host->mmc = &plat->mmc;
        if (ret)
@@ -51,10 +83,13 @@ static int arasan_sdhci_probe(struct udevice *dev)
 
 static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
 {
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
        struct sdhci_host *host = dev_get_priv(dev);
 
        host->name = dev->name;
-       host->ioaddr = dev_get_addr_ptr(dev);
+       host->ioaddr = dev_read_addr_ptr(dev);
+       host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
+#endif
 
        return 0;
 }
@@ -62,13 +97,8 @@ static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
 static int rockchip_sdhci_bind(struct udevice *dev)
 {
        struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
-       int ret;
 
-       ret = sdhci_bind(dev, &plat->mmc, &plat->cfg);
-       if (ret)
-               return ret;
-
-       return 0;
+       return sdhci_bind(dev, &plat->mmc, &plat->cfg);
 }
 
 static const struct udevice_id arasan_sdhci_ids[] = {
@@ -77,7 +107,7 @@ static const struct udevice_id arasan_sdhci_ids[] = {
 };
 
 U_BOOT_DRIVER(arasan_sdhci_drv) = {
-       .name           = "arasan_sdhci",
+       .name           = "rockchip_rk3399_sdhci_5_1",
        .id             = UCLASS_MMC,
        .of_match       = arasan_sdhci_ids,
        .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,