+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2011, Marvell Semiconductor Inc.
* Lei Wen <leiwen@marvell.com>
*
- * SPDX-License-Identifier: GPL-2.0+
- *
* Back ported to the 8xx platform (from the 8260 platform) by
* Murray.Jensen@cmst.csiro.au, 27-Jan-01.
*/
unsigned int start_addr)
{
unsigned int stat, rdy, mask, timeout, block = 0;
+ bool transfer_done = false;
#ifdef CONFIG_MMC_SDHCI_SDMA
unsigned char ctrl;
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
do {
stat = sdhci_readl(host, SDHCI_INT_STATUS);
if (stat & SDHCI_INT_ERROR) {
- printf("%s: Error detected in status(0x%X)!\n",
- __func__, stat);
+ pr_debug("%s: Error detected in status(0x%X)!\n",
+ __func__, stat);
return -EIO;
}
- if (stat & rdy) {
+ if (!transfer_done && (stat & rdy)) {
if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
continue;
sdhci_writel(host, rdy, SDHCI_INT_STATUS);
sdhci_transfer_pio(host, data);
data->dest += data->blocksize;
- if (++block >= data->blocks)
- break;
+ if (++block >= data->blocks) {
+ /* Keep looping until the SDHCI_INT_DATA_END is
+ * cleared, even if we finished sending all the
+ * blocks.
+ */
+ transfer_done = true;
+ continue;
+ }
}
#ifdef CONFIG_MMC_SDHCI_SDMA
- if (stat & SDHCI_INT_DMA_END) {
+ if (!transfer_done && (stat & SDHCI_INT_DMA_END)) {
sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
#define SDHCI_CMD_DEFAULT_TIMEOUT 100
#define SDHCI_READ_STATUS_TIMEOUT 1000
-#ifdef CONFIG_DM_MMC_OPS
+#ifdef CONFIG_DM_MMC
static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data)
{
/* Timeout unit - ms */
static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
- sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
/* We shouldn't wait for data inihibit for stop commands, even
udelay(1000);
}
+ sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
+
mask = SDHCI_INT_RESPONSE;
if (!(cmd->resp_type & MMC_RSP_PRESENT))
flags = SDHCI_CMD_RESP_NONE;
flags |= SDHCI_CMD_DATA;
/* Set Transfer mode regarding to data flag */
- if (data != 0) {
+ if (data) {
sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
mode = SDHCI_TRNS_BLK_CNT_EN;
trans_bytes = data->blocks * data->blocksize;
sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
#ifdef CONFIG_MMC_SDHCI_SDMA
- trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
- flush_cache(start_addr, trans_bytes);
+ if (data) {
+ trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
+ flush_cache(start_addr, trans_bytes);
+ }
#endif
sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
start = get_timer(0);
static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
{
struct sdhci_host *host = mmc->priv;
- unsigned int div, clk = 0, timeout, reg;
+ unsigned int div, clk = 0, timeout;
/* Wait max 20 ms */
timeout = 200;
udelay(100);
}
- reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
- reg &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
- sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
+ sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
if (clock == 0)
return 0;
*/
if (host->clk_mul) {
for (div = 1; div <= 1024; div++) {
- if ((mmc->cfg->f_max * host->clk_mul / div)
- <= clock)
+ if ((host->max_clk / div) <= clock)
break;
}
div--;
} else {
/* Version 3.00 divisors must be a multiple of 2. */
- if (mmc->cfg->f_max <= clock) {
+ if (host->max_clk <= clock) {
div = 1;
} else {
for (div = 2;
div < SDHCI_MAX_DIV_SPEC_300;
div += 2) {
- if ((mmc->cfg->f_max / div) <= clock)
+ if ((host->max_clk / div) <= clock)
break;
}
}
} else {
/* Version 2.00 divisors must be a power of 2. */
for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
- if ((mmc->cfg->f_max / div) <= clock)
+ if ((host->max_clk / div) <= clock)
break;
}
div >>= 1;
}
- if (host->ops->set_clock)
+ if (host->ops && host->ops->set_clock)
host->ops->set_clock(host, div);
clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
}
-#ifdef CONFIG_DM_MMC_OPS
+#ifdef CONFIG_DM_MMC
static int sdhci_set_ios(struct udevice *dev)
{
struct mmc *mmc = mmc_get_mmc_dev(dev);
u32 ctrl;
struct sdhci_host *host = mmc->priv;
- if (host->ops->set_control_reg)
+ if (host->ops && host->ops->set_control_reg)
host->ops->set_control_reg(host);
if (mmc->clock != host->clock)
else
ctrl &= ~SDHCI_CTRL_HISPD;
- if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
+ if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
+ (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
ctrl &= ~SDHCI_CTRL_HISPD;
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+ /* If available, call the driver specific "post" set_ios() function */
+ if (host->ops && host->ops->set_ios_post)
+ host->ops->set_ios_post(host);
+
return 0;
}
sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
- if (host->ops->get_cd)
+ if (host->ops && host->ops->get_cd)
host->ops->get_cd(host);
/* Enable only interrupts served by the SD controller */
return 0;
}
-#ifdef CONFIG_DM_MMC_OPS
+#ifdef CONFIG_DM_MMC
int sdhci_probe(struct udevice *dev)
{
struct mmc *mmc = mmc_get_mmc_dev(dev);
#endif
int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
- u32 max_clk, u32 min_clk)
+ u32 f_max, u32 f_min)
{
u32 caps, caps_1;
host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
cfg->name = host->name;
-#ifndef CONFIG_DM_MMC_OPS
+#ifndef CONFIG_DM_MMC
cfg->ops = &sdhci_ops;
#endif
- if (max_clk)
- cfg->f_max = max_clk;
- else {
+
+ /* Check whether the clock multiplier is supported or not */
+ if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
+ caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
+ host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
+ SDHCI_CLOCK_MUL_SHIFT;
+ }
+
+ if (host->max_clk == 0) {
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
- cfg->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
+ host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
SDHCI_CLOCK_BASE_SHIFT;
else
- cfg->f_max = (caps & SDHCI_CLOCK_BASE_MASK) >>
+ host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
SDHCI_CLOCK_BASE_SHIFT;
- cfg->f_max *= 1000000;
+ host->max_clk *= 1000000;
+ if (host->clk_mul)
+ host->max_clk *= host->clk_mul;
}
- if (cfg->f_max == 0) {
+ if (host->max_clk == 0) {
printf("%s: Hardware doesn't specify base clock frequency\n",
__func__);
return -EINVAL;
}
- if (min_clk)
- cfg->f_min = min_clk;
+ if (f_max && (f_max < host->max_clk))
+ cfg->f_max = f_max;
+ else
+ cfg->f_max = host->max_clk;
+ if (f_min)
+ cfg->f_min = f_min;
else {
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
cfg->voltages |= host->voltages;
- cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
+ cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
/* Since Host Controller Version3.0 */
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
if (!(caps & SDHCI_CAN_DO_8BIT))
cfg->host_caps &= ~MMC_MODE_8BIT;
+ }
- /* Find out whether clock multiplier is supported */
- caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
- host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
- SDHCI_CLOCK_MUL_SHIFT;
+ if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
+ cfg->host_caps &= ~MMC_MODE_HS;
+ cfg->host_caps &= ~MMC_MODE_HS_52MHz;
}
if (host->host_caps)
return mmc_bind(dev, mmc, cfg);
}
#else
-int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
+int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
{
int ret;
- ret = sdhci_setup_cfg(&host->cfg, host, max_clk, min_clk);
+ ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
if (ret)
return ret;
projects / u-boot / blobdiff