Revert "spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible"

[u-boot] / drivers / mtd / jedec_flash.c

diff --git a/drivers/mtd/jedec_flash.c b/drivers/mtd/jedec_flash.c
index 2350f361f1bdf2d080ac1384947b043ec0bcd3ad..ce9af8f2541210e5964073652044cd5604580c66 100644 (file)
--- a/drivers/mtd/jedec_flash.c
+++ b/drivers/mtd/jedec_flash.c
@@ -6,24 +6,7 @@
  * (C) 2000 Red Hat. GPL'd.
  * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /* The DEBUG define must be before common to enable debugging */
@@ -349,6 +332,57 @@ static const struct amd_flash_info jedec_table[] = {
                        ERASEINFO(0x10000, 15),
                }
        },
+       {
+               .mfr_id         = (u16)AMD_MANUFACT,
+               .dev_id         = AM29LV800BT,
+               .name           = "AMD AM29LV800BT",
+               .uaddr          = {
+                       [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
+               },
+               .DevSize        = SIZE_1MiB,
+               .CmdSet         = CFI_CMDSET_AMD_LEGACY,
+               .NumEraseRegions= 4,
+               .regions        = {
+                       ERASEINFO(0x10000, 15),
+                       ERASEINFO(0x08000, 1),
+                       ERASEINFO(0x02000, 2),
+                       ERASEINFO(0x04000, 1),
+               }
+       },
+       {
+               .mfr_id         = (u16)MX_MANUFACT,
+               .dev_id         = AM29LV800BT,
+               .name           = "MXIC MX29LV800BT",
+               .uaddr          = {
+                       [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
+               },
+               .DevSize        = SIZE_1MiB,
+               .CmdSet         = CFI_CMDSET_AMD_LEGACY,
+               .NumEraseRegions= 4,
+               .regions        = {
+                       ERASEINFO(0x10000, 15),
+                       ERASEINFO(0x08000, 1),
+                       ERASEINFO(0x02000, 2),
+                       ERASEINFO(0x04000, 1),
+               }
+       },
+       {
+               .mfr_id         = (u16)EON_ALT_MANU,
+               .dev_id         = AM29LV800BT,
+               .name           = "EON EN29LV800BT",
+               .uaddr          = {
+                       [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
+               },
+               .DevSize        = SIZE_1MiB,
+               .CmdSet         = CFI_CMDSET_AMD_LEGACY,
+               .NumEraseRegions= 4,
+               .regions        = {
+                       ERASEINFO(0x10000, 15),
+                       ERASEINFO(0x08000, 1),
+                       ERASEINFO(0x02000, 2),
+                       ERASEINFO(0x04000, 1),
+               }
+       },
        {
                .mfr_id         = (u16)STM_MANUFACT,
                .dev_id         = STM29F400BB,