]> git.sur5r.net Git - u-boot/blobdiff - drivers/mtd/nand/bfin_nand.c
sf: sst: setup read func
[u-boot] / drivers / mtd / nand / bfin_nand.c
index f6a0835b4b7f1b7e899a1a7953c40f8f551a99f5..3ee060f859fc9646d27a61e271a2bc08253a8541 100644 (file)
@@ -26,6 +26,7 @@
 #include <nand.h>
 
 #include <asm/blackfin.h>
+#include <asm/portmux.h>
 
 /* Bit masks for NFC_CTL */
 
@@ -75,7 +76,7 @@ static void bfin_nfc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 int bfin_nfc_devready(struct mtd_info *mtd)
 {
        pr_stamp();
-       return (bfin_read_NFC_STAT() & NBUSY ? 1 : 0);
+       return (bfin_read_NFC_STAT() & NBUSY) ? 1 : 0;
 }
 
 /*
@@ -98,6 +99,7 @@ static void bfin_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 
                /* Contents do not matter */
                bfin_write_NFC_DATA_RD(0x0000);
+               SSYNC();
 
                while (!(bfin_read_NFC_IRQSTAT() & RD_RDY))
                        if (ctrlc())
@@ -131,6 +133,11 @@ static void bfin_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len
 
                bfin_write_NFC_DATA_WR(buf[i]);
        }
+
+       /* Wait for the buffer to drain before we return */
+       while (!(bfin_read_NFC_STAT() & WB_EMPTY))
+               if (ctrlc())
+                       return;
 }
 
 /*
@@ -331,6 +338,12 @@ static struct nand_ecclayout bootrom_ecclayout = {
  */
 int board_nand_init(struct nand_chip *chip)
 {
+       const unsigned short pins[] = {
+               P_NAND_CE, P_NAND_RB, P_NAND_D0, P_NAND_D1, P_NAND_D2,
+               P_NAND_D3, P_NAND_D4, P_NAND_D5, P_NAND_D6, P_NAND_D7,
+               P_NAND_WE, P_NAND_RE, P_NAND_CLE, P_NAND_ALE, 0,
+       };
+
        pr_stamp();
 
        /* set width/ecc/timings/etc... */
@@ -341,14 +354,7 @@ int board_nand_init(struct nand_chip *chip)
        bfin_write_NFC_IRQSTAT(0xffff);
 
        /* enable GPIO function enable register */
-#ifdef __ADSPBF54x__
-       bfin_write_PORTJ_FER(bfin_read_PORTJ_FER() | 6);
-#elif defined(__ADSPBF52x__)
-       bfin_write_PORTH_FER(bfin_read_PORTH_FER() | 0xFCFF);
-       bfin_write_PORTH_MUX(0);
-#else
-# error no support for this variant
-#endif
+       peripheral_request_list(pins, "bfin_nand");
 
        chip->cmd_ctrl = bfin_nfc_cmd_ctrl;
        chip->read_buf = bfin_nfc_read_buf;