Merge branch 'master' of git://git.denx.de/u-boot-spi

[u-boot] / drivers / mtd / nand / davinci_nand.c

diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index c5a86d6c0d3f6d8cccbd3efd92c191885b1f0f77..d8bb5d3519c615cd4faa2a2fae45be02b7937cde 100644 (file)
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -16,19 +16,8 @@
  *
  * ----------------------------------------------------------------------------
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * SPDX-License-Identifier:    GPL-2.0+
  *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  * ----------------------------------------------------------------------------
  *
  *  Overview:
@@ -38,7 +27,6 @@
  Modifications:
  ver. 1.0: Feb 2005, Vinod/Sudhakar
  -
- *
  */
 
 #include <common.h>
@@ -176,35 +164,35 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
 
 #ifdef CONFIG_SYS_NAND_HW_ECC
 
-static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
+static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
 {
-       u_int32_t       val;
+       u_int32_t       ecc = 0;
 
-       (void)__raw_readl(&(davinci_emif_regs->nandfecc[
+       ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
                                CONFIG_SYS_NAND_CS - 2]));
 
-       val = __raw_readl(&davinci_emif_regs->nandfcr);
-       val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
-       val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
-       __raw_writel(val, &davinci_emif_regs->nandfcr);
+       return ecc;
 }
 
-static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
+static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
 {
-       u_int32_t       ecc = 0;
+       u_int32_t       val;
 
-       ecc = __raw_readl(&(davinci_emif_regs->nandfecc[region - 1]));
+       /* reading the ECC result register resets the ECC calculation */
+       nand_davinci_readecc(mtd);
 
-       return ecc;
+       val = __raw_readl(&davinci_emif_regs->nandfcr);
+       val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
+       val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
+       __raw_writel(val, &davinci_emif_regs->nandfcr);
 }
 
 static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
                u_char *ecc_code)
 {
        u_int32_t               tmp;
-       const int region = 1;
 
-       tmp = nand_davinci_readecc(mtd, region);
+       tmp = nand_davinci_readecc(mtd);
 
        /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
         * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
@@ -481,7 +469,8 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
         * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
         * register to 1.
         */
-       __raw_writel(1 << 13, &davinci_emif_regs->nandfcr);
+       __raw_writel(DAVINCI_NANDFCR_4BIT_CALC_START,
+                       &davinci_emif_regs->nandfcr);
 
        /*
         * Wait for the corr_state field (bits 8 to 11) in the
@@ -606,12 +595,13 @@ void davinci_nand_init(struct nand_chip *nand)
 {
        nand->chip_delay  = 0;
 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
-       nand->options     |= NAND_USE_FLASH_BBT;
+       nand->bbt_options         |= NAND_BBT_USE_FLASH;
 #endif
 #ifdef CONFIG_SYS_NAND_HW_ECC
        nand->ecc.mode = NAND_ECC_HW;
        nand->ecc.size = 512;
        nand->ecc.bytes = 3;
+       nand->ecc.strength = 1;
        nand->ecc.calculate = nand_davinci_calculate_ecc;
        nand->ecc.correct  = nand_davinci_correct_data;
        nand->ecc.hwctl  = nand_davinci_enable_hwecc;
@@ -622,6 +612,7 @@ void davinci_nand_init(struct nand_chip *nand)
        nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
        nand->ecc.size = 512;
        nand->ecc.bytes = 10;
+       nand->ecc.strength = 4;
        nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
        nand->ecc.correct = nand_davinci_4bit_correct_data;
        nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;