#define DRIVER_NAME "mxc_nand"
-typedef enum {false, true} bool;
-
struct mxc_nand_host {
struct mtd_info mtd;
struct nand_chip *nand;
.oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
};
#endif
-#elif defined(MXC_NFC_V1_1)
+#elif defined(MXC_NFC_V2_1)
#ifndef CONFIG_SYS_NAND_LARGEPAGE
static struct nand_ecclayout nand_hw_eccoob = {
.eccbytes = 9,
if (spare_only)
MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only);
- if (is_mxc_nfc_11()) {
+ if (is_mxc_nfc_21()) {
int i;
/*
* The controller copies the 64 bytes of spare data from
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, spare_only);
- if (is_mxc_nfc_11()) {
+ if (is_mxc_nfc_21()) {
int i;
/*
*/
}
-#ifdef MXC_NFC_V1_1
+#ifdef MXC_NFC_V2_1
static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
struct nand_chip *chip,
int page, int sndcmd)
case NAND_CMD_PAGEPROG:
send_prog_page(host, 0, host->spare_only);
- if (host->pagesize_2k && !is_mxc_nfc_11()) {
+ if (host->pagesize_2k && is_mxc_nfc_1()) {
/* data in 4 areas */
send_prog_page(host, 1, host->spare_only);
send_prog_page(host, 2, host->spare_only);
send_cmd(host, NAND_CMD_READSTART);
/* read for each AREA */
send_read_page(host, 0, host->spare_only);
- if (!is_mxc_nfc_11()) {
+ if (is_mxc_nfc_1()) {
send_read_page(host, 1, host->spare_only);
send_read_page(host, 2, host->spare_only);
send_read_page(host, 3, host->spare_only);
}
}
-#ifdef MXC_NFC_V1_1
-static void mxc_setup_config1(void)
-{
- uint16_t tmp;
-
- tmp = readw(&host->regs->config1);
- tmp |= NFC_ONE_CYCLE;
- tmp |= NFC_4_8N_ECC;
- writew(tmp, &host->regs->config1);
- if (host->pagesize_2k)
- writew(64/2, &host->regs->spare_area_size);
- else
- writew(16/2, &host->regs->spare_area_size);
-}
-#else
-#define mxc_setup_config1()
-#endif
-
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
int board_nand_init(struct nand_chip *this)
{
struct mtd_info *mtd;
+#ifdef MXC_NFC_V2_1
uint16_t tmp;
+#endif
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
this->options |= NAND_USE_FLASH_BBT;
this->ecc.calculate = mxc_nand_calculate_ecc;
this->ecc.hwctl = mxc_nand_enable_hwecc;
this->ecc.correct = mxc_nand_correct_data;
- if (is_mxc_nfc_11()) {
+ if (is_mxc_nfc_21()) {
this->ecc.mode = NAND_ECC_HW_SYNDROME;
this->ecc.read_page = mxc_nand_read_page_syndrome;
this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
/* Reset NAND */
this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+ /* NAND bus width determines access functions used by upper layer */
+ if (is_16bit_nand())
+ this->options |= NAND_BUSWIDTH_16;
+
+#ifdef CONFIG_SYS_NAND_LARGEPAGE
+ host->pagesize_2k = 1;
+ this->ecc.layout = &nand_hw_eccoob2k;
+#else
+ host->pagesize_2k = 0;
+ this->ecc.layout = &nand_hw_eccoob;
+#endif
+
+#ifdef MXC_NFC_V2_1
+ tmp = readw(&host->regs->config1);
+ tmp |= NFC_ONE_CYCLE;
+ tmp |= NFC_4_8N_ECC;
+ writew(tmp, &host->regs->config1);
+ if (host->pagesize_2k)
+ writew(64/2, &host->regs->spare_area_size);
+ else
+ writew(16/2, &host->regs->spare_area_size);
+#endif
+
/*
* preset operation
* Unlock the internal RAM Buffer
/* Unlock Block Command for given address range */
writew(0x4, &host->regs->wrprot);
- /* NAND bus width determines access functions used by upper layer */
- if (is_16bit_nand())
- this->options |= NAND_BUSWIDTH_16;
-
-#ifdef CONFIG_SYS_NAND_LARGEPAGE
- host->pagesize_2k = 1;
- this->ecc.layout = &nand_hw_eccoob2k;
-#else
- host->pagesize_2k = 0;
- this->ecc.layout = &nand_hw_eccoob;
-#endif
- mxc_setup_config1();
return 0;
}