Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

[u-boot] / drivers / mtd / nand / mxs_nand.c

diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index 807c9fd5f54bd43fbe725bdf077636bf2558f7ed..398e4ddc1558a8945bc53eb58b98c6c8c2fc1b4b 100644 (file)
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -25,21 +25,28 @@
  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  */
 
+#include <common.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/types.h>
-#include <common.h>
 #include <malloc.h>
 #include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/imx-common/regs-bch.h>
+#include <asm/imx-common/regs-gpmi.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/arch/dma.h>
+#include <asm/imx-common/dma.h>
 
 #define        MXS_NAND_DMA_DESCRIPTOR_COUNT           4
 
 #define        MXS_NAND_CHUNK_DATA_CHUNK_SIZE          512
+#if defined(CONFIG_MX6)
+#define        MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT    2
+#else
+#define        MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT    0
+#endif
 #define        MXS_NAND_METADATA_SIZE                  10
 
 #define        MXS_NAND_COMMAND_BUFFER_SIZE            32
@@ -237,7 +244,7 @@ static int mxs_nand_wait_for_bch_complete(void)
        int timeout = MXS_NAND_BCH_TIMEOUT;
        int ret;
 
-       ret = mx28_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
+       ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
                BCH_CTRL_COMPLETE_IRQ, timeout);
 
        writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr);
@@ -972,7 +979,7 @@ static int mxs_nand_scan_bbt(struct mtd_info *mtd)
        uint32_t tmp;
 
        /* Configure BCH and set NFC geometry */
-       mx28_reset_block(&bch_regs->hw_bch_ctrl_reg);
+       mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
 
        /* Configure layout 0 */
        tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1)
@@ -980,14 +987,16 @@ static int mxs_nand_scan_bbt(struct mtd_info *mtd)
        tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
        tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
                << BCH_FLASHLAYOUT0_ECC0_OFFSET;
-       tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
+       tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
+               >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
        writel(tmp, &bch_regs->hw_bch_flash0layout0);
 
        tmp = (mtd->writesize + mtd->oobsize)
                << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
        tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
                << BCH_FLASHLAYOUT1_ECCN_OFFSET;
-       tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
+       tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
+               >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
        writel(tmp, &bch_regs->hw_bch_flash0layout1);
 
        /* Set *all* chip selects to use layout 0 */
@@ -1058,6 +1067,8 @@ int mxs_nand_init(struct mxs_nand_info *info)
 {
        struct mxs_gpmi_regs *gpmi_regs =
                (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
+       struct mxs_bch_regs *bch_regs =
+               (struct mxs_bch_regs *)MXS_BCH_BASE;
        int i = 0, j;
 
        info->desc = malloc(sizeof(struct mxs_dma_desc *) *
@@ -1080,7 +1091,8 @@ int mxs_nand_init(struct mxs_nand_info *info)
        }
 
        /* Reset the GPMI block. */
-       mx28_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
+       mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
+       mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
 
        /*
         * Choose NAND mode, set IRQ polarity, disable write protection and