#include <linux/mtd/nand.h>
#include <linux/types.h>
#include <malloc.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
-#if defined(CONFIG_MX6)
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
#else
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
#endif
#define MXS_NAND_METADATA_SIZE 10
#define MXS_NAND_BITS_PER_ECC_LEVEL 13
+
+#if !defined(CONFIG_SYS_CACHELINE_SIZE) || CONFIG_SYS_CACHELINE_SIZE < 32
#define MXS_NAND_COMMAND_BUFFER_SIZE 32
+#else
+#define MXS_NAND_COMMAND_BUFFER_SIZE CONFIG_SYS_CACHELINE_SIZE
+#endif
#define MXS_NAND_BCH_TIMEOUT 10000
int max_ecc_strength_supported;
/* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
- if (is_cpu_type(MXC_CPU_MX6SX))
+ if (is_mx6sx() || is_mx7())
max_ecc_strength_supported = 62;
else
max_ecc_strength_supported = 40;
*/
static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
{
- struct nand_chip *nand = mtd->priv;
- struct mxs_nand_info *nand_info = nand->priv;
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
struct mxs_dma_desc *d;
uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
int ret;
*/
static int mxs_nand_device_ready(struct mtd_info *mtd)
{
- struct nand_chip *chip = mtd->priv;
- struct mxs_nand_info *nand_info = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
struct mxs_gpmi_regs *gpmi_regs =
(struct mxs_gpmi_regs *)MXS_GPMI_BASE;
uint32_t tmp;
*/
static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
{
- struct nand_chip *nand = mtd->priv;
- struct mxs_nand_info *nand_info = nand->priv;
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
nand_info->cur_chip = chip;
}
*/
static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
{
- struct nand_chip *nand = mtd->priv;
- struct mxs_nand_info *nand_info = nand->priv;
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
struct mxs_dma_desc *d;
uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
int ret;
static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
int length)
{
- struct nand_chip *nand = mtd->priv;
- struct mxs_nand_info *nand_info = nand->priv;
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
struct mxs_dma_desc *d;
uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
int ret;
uint8_t *buf, int oob_required,
int page)
{
- struct mxs_nand_info *nand_info = nand->priv;
+ struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
struct mxs_dma_desc *d;
uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
uint32_t corrected = 0, failed = 0;
*/
static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
struct nand_chip *nand, const uint8_t *buf,
- int oob_required)
+ int oob_required, int page)
{
- struct mxs_nand_info *nand_info = nand->priv;
+ struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
struct mxs_dma_desc *d;
uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
int ret;
static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
struct mtd_oob_ops *ops)
{
- struct nand_chip *chip = mtd->priv;
- struct mxs_nand_info *nand_info = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
int ret;
if (ops->mode == MTD_OPS_RAW)
static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
struct mtd_oob_ops *ops)
{
- struct nand_chip *chip = mtd->priv;
- struct mxs_nand_info *nand_info = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
int ret;
if (ops->mode == MTD_OPS_RAW)
*/
static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
{
- struct nand_chip *chip = mtd->priv;
- struct mxs_nand_info *nand_info = chip->priv;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
int ret;
nand_info->marking_block_bad = 1;
static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
int page)
{
- struct mxs_nand_info *nand_info = nand->priv;
+ struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
/*
* First, fill in the OOB buffer. If we're doing a raw read, we need to
static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
int page)
{
- struct mxs_nand_info *nand_info = nand->priv;
+ struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
uint8_t block_mark = 0;
/*
* Thus, this function is only called when we want *all* blocks to look good,
* so it *always* return success.
*/
-static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
+static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs)
{
return 0;
}
* counted, so we know the physical geometry. This enables us to make some
* important configuration decisions.
*
- * The return value of this function propogates directly back to this driver's
+ * The return value of this function propagates directly back to this driver's
* call to nand_scan(). Anything other than zero will cause this driver to
* tear everything down and declare failure.
*/
static int mxs_nand_scan_bbt(struct mtd_info *mtd)
{
- struct nand_chip *nand = mtd->priv;
- struct mxs_nand_info *nand_info = nand->priv;
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
uint32_t tmp;
(struct mxs_gpmi_regs *)MXS_GPMI_BASE;
struct mxs_bch_regs *bch_regs =
(struct mxs_bch_regs *)MXS_BCH_BASE;
- int i = 0, j;
+ int i = 0, j, ret = 0;
info->desc = malloc(sizeof(struct mxs_dma_desc *) *
MXS_NAND_DMA_DESCRIPTOR_COUNT);
- if (!info->desc)
+ if (!info->desc) {
+ ret = -ENOMEM;
goto err1;
+ }
/* Allocate the DMA descriptors. */
for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) {
info->desc[i] = mxs_dma_desc_alloc();
- if (!info->desc[i])
+ if (!info->desc[i]) {
+ ret = -ENOMEM;
goto err2;
+ }
}
/* Init the DMA controller. */
for (j = MXS_DMA_CHANNEL_AHB_APBH_GPMI0;
j <= MXS_DMA_CHANNEL_AHB_APBH_GPMI7; j++) {
- if (mxs_dma_init_channel(j))
+ ret = mxs_dma_init_channel(j);
+ if (ret)
goto err3;
}
return 0;
err3:
- for (--j; j >= 0; j--)
+ for (--j; j >= MXS_DMA_CHANNEL_AHB_APBH_GPMI0; j--)
mxs_dma_release(j);
err2:
- free(info->desc);
-err1:
for (--i; i >= 0; i--)
mxs_dma_desc_free(info->desc[i]);
- printf("MXS NAND: Unable to allocate DMA descriptors\n");
- return -ENOMEM;
+ free(info->desc);
+err1:
+ if (ret == -ENOMEM)
+ printf("MXS NAND: Unable to allocate DMA descriptors\n");
+ return ret;
}
/*!
memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
- nand->priv = nand_info;
+ nand_set_controller_data(nand, nand_info);
nand->options |= NAND_NO_SUBPAGE_WRITE;
nand->cmd_ctrl = mxs_nand_cmd_ctrl;
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