+// SPDX-License-Identifier: GPL-2.0+
/*
* Freescale i.MX28 NAND flash driver
*
*
* Copyright (C) 2010 Freescale Semiconductor, Inc.
* Copyright (C) 2008 Embedded Alley Solutions, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/rawnand.h>
+#include <linux/sizes.h>
#include <linux/types.h>
#include <malloc.h>
+#include <nand.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/regs-gpmi.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/dma.h>
+#include "mxs_nand.h"
#define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
-#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
#else
#define MXS_NAND_BCH_TIMEOUT 10000
+/**
+ * @gf_len: The length of Galois Field. (e.g., 13 or 14)
+ * @ecc_strength: A number that describes the strength of the ECC
+ * algorithm.
+ * @ecc_chunk_size: The size, in bytes, of a single ECC chunk. Note
+ * the first chunk in the page includes both data and
+ * metadata, so it's a bit larger than this value.
+ * @ecc_chunk_count: The number of ECC chunks in the page,
+ * @block_mark_byte_offset: The byte offset in the ECC-based page view at
+ * which the underlying physical block mark appears.
+ * @block_mark_bit_offset: The bit offset into the ECC-based page view at
+ * which the underlying physical block mark appears.
+ */
+struct bch_geometry {
+ unsigned int gf_len;
+ unsigned int ecc_strength;
+ unsigned int ecc_chunk_size;
+ unsigned int ecc_chunk_count;
+ unsigned int block_mark_byte_offset;
+ unsigned int block_mark_bit_offset;
+};
+
struct mxs_nand_info {
+ struct nand_chip chip;
int cur_chip;
uint32_t cmd_queue_len;
uint32_t data_buf_size;
+ struct bch_geometry bch_geometry;
uint8_t *cmd_buf;
uint8_t *data_buf;
uint8_t marking_block_bad;
uint8_t raw_oob_mode;
+ struct mxs_gpmi_regs *gpmi_regs;
+ struct mxs_bch_regs *bch_regs;
+
/* Functions with altered behaviour */
int (*hooked_read_oob)(struct mtd_info *mtd,
loff_t from, struct mtd_oob_ops *ops);
};
struct nand_ecclayout fake_ecc_layout;
-static int chunk_data_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
-static int galois_field = 13;
/*
* Cache management functions
info->desc_index = 0;
}
-static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size)
-{
- return page_data_size / chunk_data_size;
-}
-
-static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength)
-{
- return ecc_strength * galois_field;
-}
-
static uint32_t mxs_nand_aux_status_offset(void)
{
return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3;
}
-static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
- uint32_t page_oob_size)
-{
- int ecc_strength;
- int max_ecc_strength_supported;
-
- /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
- if (is_mx6sx() || is_mx7())
- max_ecc_strength_supported = 62;
- else
- max_ecc_strength_supported = 40;
-
- /*
- * Determine the ECC layout with the formula:
- * ECC bits per chunk = (total page spare data bits) /
- * (bits per ECC level) / (chunks per page)
- * where:
- * total page spare data bits =
- * (page oob size - meta data size) * (bits per byte)
- */
- ecc_strength = ((page_oob_size - MXS_NAND_METADATA_SIZE) * 8)
- / (galois_field *
- mxs_nand_ecc_chunk_cnt(page_data_size));
-
- return min(round_down(ecc_strength, 2), max_ecc_strength_supported);
-}
-
-static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
- uint32_t ecc_strength)
+static inline int mxs_nand_calc_mark_offset(struct bch_geometry *geo,
+ uint32_t page_data_size)
{
- uint32_t chunk_data_size_in_bits;
- uint32_t chunk_ecc_size_in_bits;
+ uint32_t chunk_data_size_in_bits = geo->ecc_chunk_size * 8;
+ uint32_t chunk_ecc_size_in_bits = geo->ecc_strength * geo->gf_len;
uint32_t chunk_total_size_in_bits;
uint32_t block_mark_chunk_number;
uint32_t block_mark_chunk_bit_offset;
uint32_t block_mark_bit_offset;
- chunk_data_size_in_bits = chunk_data_size * 8;
- chunk_ecc_size_in_bits = mxs_nand_ecc_size_in_bits(ecc_strength);
-
chunk_total_size_in_bits =
chunk_data_size_in_bits + chunk_ecc_size_in_bits;
(block_mark_chunk_number * chunk_total_size_in_bits);
if (block_mark_chunk_bit_offset > chunk_data_size_in_bits)
- return 1;
+ return -EINVAL;
/*
* Now that we know the chunk number in which the block mark appears,
block_mark_bit_offset -=
block_mark_chunk_number * chunk_ecc_size_in_bits;
- return block_mark_bit_offset;
+ geo->block_mark_byte_offset = block_mark_bit_offset >> 3;
+ geo->block_mark_bit_offset = block_mark_bit_offset & 0x7;
+
+ return 0;
+}
+
+static inline unsigned int mxs_nand_max_ecc_strength_supported(void)
+{
+ /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
+ if (is_mx6sx() || is_mx7())
+ return 62;
+ else
+ return 40;
}
-static uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd)
+static inline int mxs_nand_calc_ecc_layout_by_info(struct bch_geometry *geo,
+ struct mtd_info *mtd)
{
- uint32_t ecc_strength;
- ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
- return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) >> 3;
+ struct nand_chip *chip = mtd_to_nand(mtd);
+
+ if (!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0))
+ return -ENOTSUPP;
+
+ switch (chip->ecc_step_ds) {
+ case SZ_512:
+ geo->gf_len = 13;
+ break;
+ case SZ_1K:
+ geo->gf_len = 14;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ geo->ecc_chunk_size = chip->ecc_step_ds;
+ geo->ecc_strength = round_up(chip->ecc_strength_ds, 2);
+
+ /* Keep the C >= O */
+ if (geo->ecc_chunk_size < mtd->oobsize)
+ return -EINVAL;
+
+ if (geo->ecc_strength > mxs_nand_max_ecc_strength_supported())
+ return -EINVAL;
+
+ geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size;
+
+ return 0;
}
-static uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd)
+static inline int mxs_nand_calc_ecc_layout(struct bch_geometry *geo,
+ struct mtd_info *mtd)
{
- uint32_t ecc_strength;
- ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
- return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) & 0x7;
+ /* The default for the length of Galois Field. */
+ geo->gf_len = 13;
+
+ /* The default for chunk size. */
+ geo->ecc_chunk_size = 512;
+
+ if (geo->ecc_chunk_size < mtd->oobsize) {
+ geo->gf_len = 14;
+ geo->ecc_chunk_size *= 2;
+ }
+
+ if (mtd->oobsize > geo->ecc_chunk_size) {
+ printf("Not support the NAND chips whose oob size is larger then %d bytes!\n",
+ geo->ecc_chunk_size);
+ return -EINVAL;
+ }
+
+ geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size;
+
+ /*
+ * Determine the ECC layout with the formula:
+ * ECC bits per chunk = (total page spare data bits) /
+ * (bits per ECC level) / (chunks per page)
+ * where:
+ * total page spare data bits =
+ * (page oob size - meta data size) * (bits per byte)
+ */
+ geo->ecc_strength = ((mtd->oobsize - MXS_NAND_METADATA_SIZE) * 8)
+ / (geo->gf_len * geo->ecc_chunk_count);
+
+ geo->ecc_strength = min(round_down(geo->ecc_strength, 2),
+ mxs_nand_max_ecc_strength_supported());
+
+ return 0;
}
/*
* Wait for BCH complete IRQ and clear the IRQ
*/
-static int mxs_nand_wait_for_bch_complete(void)
+static int mxs_nand_wait_for_bch_complete(struct mxs_nand_info *nand_info)
{
- struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
int timeout = MXS_NAND_BCH_TIMEOUT;
int ret;
- ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
+ ret = mxs_wait_mask_set(&nand_info->bch_regs->hw_bch_ctrl_reg,
BCH_CTRL_COMPLETE_IRQ, timeout);
- writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr);
+ writel(BCH_CTRL_COMPLETE_IRQ, &nand_info->bch_regs->hw_bch_ctrl_clr);
return ret;
}
{
struct nand_chip *chip = mtd_to_nand(mtd);
struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
- struct mxs_gpmi_regs *gpmi_regs =
- (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
uint32_t tmp;
- tmp = readl(&gpmi_regs->hw_gpmi_stat);
+ tmp = readl(&nand_info->gpmi_regs->hw_gpmi_stat);
tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
return tmp & 1;
* swapping the block mark, or swapping it *back* -- but it doesn't matter
* because the the operation is the same.
*/
-static void mxs_nand_swap_block_mark(struct mtd_info *mtd,
- uint8_t *data_buf, uint8_t *oob_buf)
+static void mxs_nand_swap_block_mark(struct bch_geometry *geo,
+ uint8_t *data_buf, uint8_t *oob_buf)
{
- uint32_t bit_offset;
- uint32_t buf_offset;
+ uint32_t bit_offset = geo->block_mark_bit_offset;
+ uint32_t buf_offset = geo->block_mark_byte_offset;
uint32_t src;
uint32_t dst;
- bit_offset = mxs_nand_mark_bit_offset(mtd);
- buf_offset = mxs_nand_mark_byte_offset(mtd);
-
/*
* Get the byte from the data area that overlays the block mark. Since
* the ECC engine applies its own view to the bits in the page, the
int page)
{
struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
+ struct bch_geometry *geo = &nand_info->bch_geometry;
struct mxs_dma_desc *d;
uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
uint32_t corrected = 0, failed = 0;
goto rtn;
}
- ret = mxs_nand_wait_for_bch_complete();
+ ret = mxs_nand_wait_for_bch_complete(nand_info);
if (ret) {
printf("MXS NAND: BCH read timeout\n");
goto rtn;
mxs_nand_inval_data_buf(nand_info);
/* Read DMA completed, now do the mark swapping. */
- mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
+ mxs_nand_swap_block_mark(geo, nand_info->data_buf, nand_info->oob_buf);
/* Loop over status bytes, accumulating ECC status. */
status = nand_info->oob_buf + mxs_nand_aux_status_offset();
- for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd->writesize); i++) {
+ for (i = 0; i < geo->ecc_chunk_count; i++) {
if (status[i] == 0x00)
continue;
int oob_required, int page)
{
struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
+ struct bch_geometry *geo = &nand_info->bch_geometry;
struct mxs_dma_desc *d;
uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
int ret;
memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);
/* Handle block mark swapping. */
- mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
+ mxs_nand_swap_block_mark(geo, nand_info->data_buf, nand_info->oob_buf);
/* Compile the DMA descriptor - write data. */
d = mxs_nand_get_dma_desc(nand_info);
goto rtn;
}
- ret = mxs_nand_wait_for_bch_complete();
+ ret = mxs_nand_wait_for_bch_complete(nand_info);
if (ret) {
printf("MXS NAND: BCH write timeout\n");
goto rtn;
}
/*
- * Nominally, the purpose of this function is to look for or create the bad
- * block table. In fact, since the we call this function at the very end of
- * the initialization process started by nand_scan(), and we doesn't have a
- * more formal mechanism, we "hook" this function to continue init process.
- *
* At this point, the physical NAND Flash chips have been identified and
* counted, so we know the physical geometry. This enables us to make some
* important configuration decisions.
*
* The return value of this function propagates directly back to this driver's
- * call to nand_scan(). Anything other than zero will cause this driver to
+ * board_nand_init(). Anything other than zero will cause this driver to
* tear everything down and declare failure.
*/
-static int mxs_nand_scan_bbt(struct mtd_info *mtd)
+int mxs_nand_setup_ecc(struct mtd_info *mtd)
{
struct nand_chip *nand = mtd_to_nand(mtd);
struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
- struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
+ struct bch_geometry *geo = &nand_info->bch_geometry;
+ struct mxs_bch_regs *bch_regs = nand_info->bch_regs;
uint32_t tmp;
+ int ret = -ENOTSUPP;
- if (mtd->oobsize > MXS_NAND_CHUNK_DATA_CHUNK_SIZE) {
- galois_field = 14;
- chunk_data_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 2;
- }
+#ifdef CONFIG_NAND_MXS_USE_MINIMUM_ECC
+ ret = mxs_nand_calc_ecc_layout_by_info(geo, mtd);
+#endif
- if (mtd->oobsize > chunk_data_size) {
- printf("Not support the NAND chips whose oob size is larger then %d bytes!\n", chunk_data_size);
- return -EINVAL;
- }
+ if (ret == -ENOTSUPP)
+ ret = mxs_nand_calc_ecc_layout(geo, mtd);
+
+ if (ret)
+ return ret;
+
+ mxs_nand_calc_mark_offset(geo, mtd->writesize);
/* Configure BCH and set NFC geometry */
mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
/* Configure layout 0 */
- tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1)
- << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
+ tmp = (geo->ecc_chunk_count - 1) << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
- tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
- << BCH_FLASHLAYOUT0_ECC0_OFFSET;
- tmp |= chunk_data_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
- tmp |= (14 == galois_field ? 1 : 0) <<
+ tmp |= (geo->ecc_strength >> 1) << BCH_FLASHLAYOUT0_ECC0_OFFSET;
+ tmp |= geo->ecc_chunk_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
+ tmp |= (geo->gf_len == 14 ? 1 : 0) <<
BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET;
writel(tmp, &bch_regs->hw_bch_flash0layout0);
tmp = (mtd->writesize + mtd->oobsize)
<< BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
- tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
- << BCH_FLASHLAYOUT1_ECCN_OFFSET;
- tmp |= chunk_data_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
- tmp |= (14 == galois_field ? 1 : 0) <<
+ tmp |= (geo->ecc_strength >> 1) << BCH_FLASHLAYOUT1_ECCN_OFFSET;
+ tmp |= geo->ecc_chunk_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
+ tmp |= (geo->gf_len == 14 ? 1 : 0) <<
BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET;
writel(tmp, &bch_regs->hw_bch_flash0layout1);
mtd->_block_markbad = mxs_nand_hook_block_markbad;
}
- /* We use the reference implementation for bad block management. */
- return nand_default_bbt(mtd);
+ return 0;
}
/*
/*
* Initializes the NFC hardware.
*/
-int mxs_nand_init(struct mxs_nand_info *info)
+int mxs_nand_init_dma(struct mxs_nand_info *info)
{
- struct mxs_gpmi_regs *gpmi_regs =
- (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
- struct mxs_bch_regs *bch_regs =
- (struct mxs_bch_regs *)MXS_BCH_BASE;
int i = 0, j, ret = 0;
info->desc = malloc(sizeof(struct mxs_dma_desc *) *
}
/* Reset the GPMI block. */
- mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
- mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
+ mxs_reset_block(&info->gpmi_regs->hw_gpmi_ctrl0_reg);
+ mxs_reset_block(&info->bch_regs->hw_bch_ctrl_reg);
/*
* Choose NAND mode, set IRQ polarity, disable write protection and
* select BCH ECC.
*/
- clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1,
+ clrsetbits_le32(&info->gpmi_regs->hw_gpmi_ctrl1,
GPMI_CTRL1_GPMI_MODE,
GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
GPMI_CTRL1_BCH_MODE);
return ret;
}
-/*!
- * This function is called during the driver binding process.
- *
- * @param pdev the device structure used to store device specific
- * information that is used by the suspend, resume and
- * remove functions
- *
- * @return The function always returns 0.
- */
-int board_nand_init(struct nand_chip *nand)
+int mxs_nand_init_spl(struct nand_chip *nand)
{
struct mxs_nand_info *nand_info;
int err;
}
memset(nand_info, 0, sizeof(struct mxs_nand_info));
+ nand_info->gpmi_regs = (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
+ nand_info->bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
err = mxs_nand_alloc_buffers(nand_info);
if (err)
- goto err1;
+ return err;
- err = mxs_nand_init(nand_info);
+ err = mxs_nand_init_dma(nand_info);
if (err)
- goto err2;
+ return err;
+
+ nand_set_controller_data(nand, nand_info);
+
+ nand->options |= NAND_NO_SUBPAGE_WRITE;
+
+ nand->cmd_ctrl = mxs_nand_cmd_ctrl;
+ nand->dev_ready = mxs_nand_device_ready;
+ nand->select_chip = mxs_nand_select_chip;
+
+ nand->read_byte = mxs_nand_read_byte;
+ nand->read_buf = mxs_nand_read_buf;
+
+ nand->ecc.read_page = mxs_nand_ecc_read_page;
+
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.bytes = 9;
+ nand->ecc.size = 512;
+ nand->ecc.strength = 8;
+
+ return 0;
+}
+
+int mxs_nand_init(struct mxs_nand_info *nand_info)
+{
+ struct mtd_info *mtd;
+ struct nand_chip *nand;
+ int err;
+
+ nand = &nand_info->chip;
+ mtd = nand_to_mtd(nand);
+ err = mxs_nand_alloc_buffers(nand_info);
+ if (err)
+ return err;
+
+ err = mxs_nand_init_dma(nand_info);
+ if (err)
+ goto err_free_buffers;
memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
+ nand->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
+#endif
+
nand_set_controller_data(nand, nand_info);
nand->options |= NAND_NO_SUBPAGE_WRITE;
nand->dev_ready = mxs_nand_device_ready;
nand->select_chip = mxs_nand_select_chip;
nand->block_bad = mxs_nand_block_bad;
- nand->scan_bbt = mxs_nand_scan_bbt;
nand->read_byte = mxs_nand_read_byte;
nand->read_buf = mxs_nand_read_buf;
nand->write_buf = mxs_nand_write_buf;
+ /* first scan to find the device and get the page size */
+ if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL))
+ goto err_free_buffers;
+
+ if (mxs_nand_setup_ecc(mtd))
+ goto err_free_buffers;
+
nand->ecc.read_page = mxs_nand_ecc_read_page;
nand->ecc.write_page = mxs_nand_ecc_write_page;
nand->ecc.read_oob = mxs_nand_ecc_read_oob;
nand->ecc.layout = &fake_ecc_layout;
nand->ecc.mode = NAND_ECC_HW;
- nand->ecc.bytes = 9;
- nand->ecc.size = 512;
- nand->ecc.strength = 8;
+ nand->ecc.size = nand_info->bch_geometry.ecc_chunk_size;
+ nand->ecc.strength = nand_info->bch_geometry.ecc_strength;
+
+ /* second phase scan */
+ err = nand_scan_tail(mtd);
+ if (err)
+ goto err_free_buffers;
+
+ err = nand_register(0, mtd);
+ if (err)
+ goto err_free_buffers;
return 0;
-err2:
+err_free_buffers:
free(nand_info->data_buf);
free(nand_info->cmd_buf);
-err1:
- free(nand_info);
+
return err;
}
+
+void board_nand_init(void)
+{
+ struct mxs_nand_info *nand_info;
+
+ nand_info = malloc(sizeof(struct mxs_nand_info));
+ if (!nand_info) {
+ printf("MXS NAND: Failed to allocate private data\n");
+ return;
+ }
+ memset(nand_info, 0, sizeof(struct mxs_nand_info));
+
+ nand_info->gpmi_regs = (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
+ nand_info->bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
+
+ if (mxs_nand_init(nand_info) < 0)
+ goto err;
+
+ return;
+
+err:
+ free(nand_info);
+}
projects / u-boot / blobdiff