]> git.sur5r.net Git - u-boot/blobdiff - drivers/mtd/nand/ndfc.c
mtd, omap: fix case NAND_OMAP_GPMC_PREFETCH not defined
[u-boot] / drivers / mtd / nand / ndfc.c
index 34688e9bef43231caac3f709a9f5a5f4165ae721..265959502d8320a0533d59eb4be88528984518a8 100644 (file)
@@ -104,7 +104,6 @@ static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
                *p++ = in_be32((u32 *)(base + NDFC_DATA));
 }
 
-#ifndef CONFIG_NAND_SPL
 /*
  * Don't use these speedup functions in NAND boot image, since the image
  * has to fit into 4kByte.
@@ -119,6 +118,7 @@ static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len
                out_be32((u32 *)(base + NDFC_DATA), *p++);
 }
 
+#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
 static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
 {
        struct nand_chip *this = mtdinfo->priv;
@@ -131,6 +131,7 @@ static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len
 
        return 0;
 }
+#endif
 
 /*
  * Read a byte from the NDFC.
@@ -148,8 +149,6 @@ static uint8_t ndfc_read_byte(struct mtd_info *mtd)
 
 }
 
-#endif /* #ifndef CONFIG_NAND_SPL */
-
 void board_nand_select_device(struct nand_chip *nand, int chip)
 {
        /*
@@ -207,21 +206,13 @@ int board_nand_init(struct nand_chip *nand)
        nand->options |= NAND_BUSWIDTH_16;
 #endif
 
-#ifndef CONFIG_NAND_SPL
        nand->write_buf  = ndfc_write_buf;
+#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
        nand->verify_buf = ndfc_verify_buf;
+#endif
        nand->read_byte = ndfc_read_byte;
 
        chip++;
-#else
-       /*
-        * Setup EBC (CS0 only right now)
-        */
-       mtebc(EBC0_CFG, CONFIG_SYS_NDFC_EBC0_CFG);
-
-       mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR);
-       mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP);
-#endif
 
        return 0;
 }