Move ALLOC_CACHE_ALIGN_BUFFER() to the new memalign.h header

[u-boot] / drivers / mtd / nand / ndfc.c

diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c
index 34688e9bef43231caac3f709a9f5a5f4165ae721..8a68cb0a67a7fc226e1f805097561667b196d2c4 100644 (file)
--- a/drivers/mtd/nand/ndfc.c
+++ b/drivers/mtd/nand/ndfc.c
@@ -104,7 +104,6 @@ static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
                *p++ = in_be32((u32 *)(base + NDFC_DATA));
 }
 
-#ifndef CONFIG_NAND_SPL
 /*
  * Don't use these speedup functions in NAND boot image, since the image
  * has to fit into 4kByte.
@@ -119,19 +118,6 @@ static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len
                out_be32((u32 *)(base + NDFC_DATA), *p++);
 }
 
-static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
-{
-       struct nand_chip *this = mtdinfo->priv;
-       ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
-       uint32_t *p = (uint32_t *) buf;
-
-       for (; len > 0; len -= 4)
-               if (*p++ != in_be32((u32 *)(base + NDFC_DATA)))
-                       return -1;
-
-       return 0;
-}
-
 /*
  * Read a byte from the NDFC.
  */
@@ -148,8 +134,6 @@ static uint8_t ndfc_read_byte(struct mtd_info *mtd)
 
 }
 
-#endif /* #ifndef CONFIG_NAND_SPL */
-
 void board_nand_select_device(struct nand_chip *nand, int chip)
 {
        /*
@@ -207,21 +191,10 @@ int board_nand_init(struct nand_chip *nand)
        nand->options |= NAND_BUSWIDTH_16;
 #endif
 
-#ifndef CONFIG_NAND_SPL
        nand->write_buf  = ndfc_write_buf;
-       nand->verify_buf = ndfc_verify_buf;
        nand->read_byte = ndfc_read_byte;
 
        chip++;
-#else
-       /*
-        * Setup EBC (CS0 only right now)
-        */
-       mtebc(EBC0_CFG, CONFIG_SYS_NDFC_EBC0_CFG);
-
-       mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR);
-       mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP);
-#endif
 
        return 0;
 }