SPDX: Convert all of our single license tags to Linux Kernel style

[u-boot] / drivers / mtd / nand / zynq_nand.c

diff --git a/drivers/mtd/nand/zynq_nand.c b/drivers/mtd/nand/zynq_nand.c
index cb3340d9b09c1c313121abc41ecab96ccae113e4..efd3c9b7987eff4838cadf9f1b0b37cdaba951d6 100644 (file)
--- a/drivers/mtd/nand/zynq_nand.c
+++ b/drivers/mtd/nand/zynq_nand.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2016 Xilinx, Inc.
  *
  * Xilinx Zynq NAND Flash Controller Driver
  * This driver is based on plat_nand.c and mxc_nand.c drivers
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -13,7 +12,7 @@
 #include <linux/errno.h>
 #include <nand.h>
 #include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
+#include <linux/mtd/rawnand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand_ecc.h>
 #include <asm/arch/hardware.h>
@@ -35,6 +34,8 @@
                                (0x1 << 4)   |  /* Clear interrupt */ \
                                (0x1 << 6))     /* Disable ECC interrupt */
 
+#ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
+
 /* Assuming 50MHz clock (20ns cycle time) and 3V operation */
 #define ZYNQ_NAND_SET_CYCLES   ((0x2 << 20) |  /* t_rr from nand_cycles */ \
                                (0x2 << 17)  |  /* t_ar from nand_cycles */ \
@@ -43,6 +44,7 @@
                                (0x2 << 8)   |  /* t_rea from nand_cycles */ \
                                (0x5 << 4)   |  /* t_wc from nand_cycles */ \
                                (0x5 << 0))     /* t_rc from nand_cycles */
+#endif
 
 
 #define ZYNQ_NAND_DIRECT_CMD   ((0x4 << 23) |  /* Chip 0 from interface 1 */ \
@@ -81,6 +83,13 @@
 #define ZYNQ_NAND_ECC_BUSY     (1 << 6)        /* ECC block is busy */
 #define ZYNQ_NAND_ECC_MASK     0x00FFFFFF      /* ECC value mask */
 
+#ifndef NAND_CMD_LOCK_TIGHT
+#define NAND_CMD_LOCK_TIGHT 0x2c
+#endif
+
+#ifndef NAND_CMD_LOCK_STATUS
+#define NAND_CMD_LOCK_STATUS 0x7a
+#endif
 
 /* SMC register set */
 struct zynq_nand_smc_regs {
@@ -141,6 +150,11 @@ static const struct zynq_nand_command_format zynq_nand_commands[] = {
        {NAND_CMD_PARAM, NAND_CMD_NONE, 1, 0},
        {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 0},
        {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0},
+       {NAND_CMD_LOCK, NAND_CMD_NONE, 0, 0},
+       {NAND_CMD_LOCK_TIGHT, NAND_CMD_NONE, 0, 0},
+       {NAND_CMD_UNLOCK1, NAND_CMD_NONE, 3, 0},
+       {NAND_CMD_UNLOCK2, NAND_CMD_NONE, 3, 0},
+       {NAND_CMD_LOCK_STATUS, NAND_CMD_NONE, 3, 0},
        {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0},
        /* Add all the flash commands supported by the flash device */
 };
@@ -245,8 +259,10 @@ static int zynq_nand_init_nand_flash(int option)
 
        /* disable interrupts */
        writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr);
+#ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
        /* Initialize the NAND interface by setting cycles and operation mode */
        writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr);
+#endif
        if (option & NAND_BUSWIDTH_16)
                writel(ZYNQ_NAND_SET_OPMODE_16BIT, &zynq_nand_smc_base->sor);
        else
@@ -1008,7 +1024,7 @@ static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
        }
 
        xnand->nand_base = (void __iomem *)ZYNQ_NAND_BASEADDR;
-       mtd = (struct mtd_info *)&nand_info[0];
+       mtd = nand_to_mtd(nand_chip);
 
        nand_chip->priv = xnand;
        mtd->priv = nand_chip;