+// SPDX-License-Identifier: GPL-2.0+
/*
* SPI Flash Core
*
* Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
* Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
* Copyright (C) 2008 Atmel Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spi.h>
#include <spi_flash.h>
#include <linux/log2.h>
+#include <linux/sizes.h>
+#include <dma.h>
#include "sf_internal.h"
-DECLARE_GLOBAL_DATA_PTR;
-
static void spi_flash_addr(u32 addr, u8 *cmd)
{
/* cmd[0] is actual command */
}
#endif
-#ifdef CONFIG_SPI_FLASH_STMICRO
-static int read_evcr(struct spi_flash *flash, u8 *evcr)
-{
- int ret;
- const u8 cmd = CMD_READ_EVCR;
-
- ret = spi_flash_read_common(flash, &cmd, 1, evcr, 1);
- if (ret < 0) {
- debug("SF: error reading EVCR\n");
- return ret;
- }
-
- return 0;
-}
-
-static int write_evcr(struct spi_flash *flash, u8 evcr)
+#ifdef CONFIG_SPI_FLASH_BAR
+/*
+ * This "clean_bar" is necessary in a situation when one was accessing
+ * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
+ *
+ * After it the BA24 bit shall be cleared to allow access to correct
+ * memory region after SW reset (by calling "reset" command).
+ *
+ * Otherwise, the BA24 bit may be left set and then after reset, the
+ * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
+ */
+static int clean_bar(struct spi_flash *flash)
{
- u8 cmd;
- int ret;
+ u8 cmd, bank_sel = 0;
- cmd = CMD_WRITE_EVCR;
- ret = spi_flash_write_common(flash, &cmd, 1, &evcr, 1);
- if (ret < 0) {
- debug("SF: error while writing EVCR register\n");
- return ret;
- }
+ if (flash->bank_curr == 0)
+ return 0;
+ cmd = flash->bank_write_cmd;
- return 0;
+ return spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
}
-#endif
-#ifdef CONFIG_SPI_FLASH_BAR
-static int spi_flash_write_bar(struct spi_flash *flash, u32 offset)
+static int write_bar(struct spi_flash *flash, u32 offset)
{
u8 cmd, bank_sel;
int ret;
return flash->bank_curr;
}
-static int spi_flash_read_bar(struct spi_flash *flash, u8 idcode0)
+static int read_bar(struct spi_flash *flash, const struct spi_flash_info *info)
{
u8 curr_bank = 0;
int ret;
if (flash->size <= SPI_FLASH_16MB_BOUN)
goto bar_end;
- switch (idcode0) {
+ switch (JEDEC_MFR(info)) {
case SPI_FLASH_CFI_MFR_SPANSION:
flash->bank_read_cmd = CMD_BANKADDR_BRRD;
flash->bank_write_cmd = CMD_BANKADDR_BRWR;
#ifdef CONFIG_SF_DUAL_FLASH
static void spi_flash_dual(struct spi_flash *flash, u32 *addr)
{
- struct spi_slave *spi = flash->spi;
-
switch (flash->dual_flash) {
case SF_DUAL_STACKED_FLASH:
if (*addr >= (flash->size >> 1)) {
*addr -= flash->size >> 1;
- spi->flags |= SPI_XFER_U_PAGE;
+ flash->flags |= SNOR_F_USE_UPAGE;
} else {
- spi->flags &= ~SPI_XFER_U_PAGE;
+ flash->flags &= ~SNOR_F_USE_UPAGE;
}
break;
case SF_DUAL_PARALLEL_FLASH:
return sr && fsr;
}
-static int spi_flash_cmd_wait_ready(struct spi_flash *flash,
- unsigned long timeout)
+static int spi_flash_wait_till_ready(struct spi_flash *flash,
+ unsigned long timeout)
{
- int timebase, ret;
+ unsigned long timebase;
+ int ret;
timebase = get_timer(0);
return ret;
}
- ret = spi_flash_cmd_wait_ready(flash, timeout);
+ ret = spi_flash_wait_till_ready(flash, timeout);
if (ret < 0) {
debug("SF: write %s timed out\n",
timeout == SPI_FLASH_PROG_TIMEOUT ?
erase_size = flash->erase_size;
if (offset % erase_size || len % erase_size) {
- debug("SF: Erase offset/length not multiple of erase size\n");
+ printf("SF: Erase offset/length not multiple of erase size\n");
return -1;
}
spi_flash_dual(flash, &erase_addr);
#endif
#ifdef CONFIG_SPI_FLASH_BAR
- ret = spi_flash_write_bar(flash, erase_addr);
+ ret = write_bar(flash, erase_addr);
if (ret < 0)
return ret;
#endif
len -= erase_size;
}
+#ifdef CONFIG_SPI_FLASH_BAR
+ ret = clean_bar(flash);
+#endif
+
return ret;
}
spi_flash_dual(flash, &write_addr);
#endif
#ifdef CONFIG_SPI_FLASH_BAR
- ret = spi_flash_write_bar(flash, write_addr);
+ ret = write_bar(flash, write_addr);
if (ret < 0)
return ret;
#endif
if (spi->max_write_size)
chunk_len = min(chunk_len,
- (size_t)spi->max_write_size);
+ spi->max_write_size - sizeof(cmd));
spi_flash_addr(write_addr, cmd);
offset += chunk_len;
}
+#ifdef CONFIG_SPI_FLASH_BAR
+ ret = clean_bar(flash);
+#endif
+
return ret;
}
return ret;
}
+/*
+ * TODO: remove the weak after all the other spi_flash_copy_mmap
+ * implementations removed from drivers
+ */
void __weak spi_flash_copy_mmap(void *data, void *offset, size_t len)
{
+#ifdef CONFIG_DMA
+ if (!dma_memcpy(data, offset, len))
+ return;
+#endif
memcpy(data, offset, len);
}
spi_flash_dual(flash, &read_addr);
#endif
#ifdef CONFIG_SPI_FLASH_BAR
- ret = spi_flash_write_bar(flash, read_addr);
+ ret = write_bar(flash, read_addr);
if (ret < 0)
return ret;
bank_sel = flash->bank_curr;
else
read_len = remain_len;
+ if (spi->max_read_size)
+ read_len = min(read_len, spi->max_read_size);
+
spi_flash_addr(read_addr, cmd);
ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
data += read_len;
}
+#ifdef CONFIG_SPI_FLASH_BAR
+ ret = clean_bar(flash);
+#endif
+
free(cmd);
return ret;
}
#ifdef CONFIG_SPI_FLASH_SST
+static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl)
+{
+ switch (ctl) {
+ case SST26_CTL_LOCK:
+ cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8);
+ break;
+ case SST26_CTL_UNLOCK:
+ cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8);
+ break;
+ case SST26_CTL_CHECK:
+ return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8));
+ }
+
+ return false;
+}
+
+/*
+ * sst26wf016/sst26wf032/sst26wf064 have next block protection:
+ * 4x - 8 KByte blocks - read & write protection bits - upper addresses
+ * 1x - 32 KByte blocks - write protection bits
+ * rest - 64 KByte blocks - write protection bits
+ * 1x - 32 KByte blocks - write protection bits
+ * 4x - 8 KByte blocks - read & write protection bits - lower addresses
+ *
+ * We'll support only per 64k lock/unlock so lower and upper 64 KByte region
+ * will be treated as single block.
+ */
+
+/*
+ * Lock, unlock or check lock status of the flash region of the flash (depending
+ * on the lock_ctl value)
+ */
+static int sst26_lock_ctl(struct spi_flash *flash, u32 ofs, size_t len, enum lock_ctl ctl)
+{
+ u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size;
+ bool lower_64k = false, upper_64k = false;
+ u8 cmd, bpr_buff[SST26_MAX_BPR_REG_LEN] = {};
+ int ret;
+
+ /* Check length and offset for 64k alignment */
+ if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1)))
+ return -EINVAL;
+
+ if (ofs + len > flash->size)
+ return -EINVAL;
+
+ /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */
+ if (flash->size != SZ_2M &&
+ flash->size != SZ_4M &&
+ flash->size != SZ_8M)
+ return -EINVAL;
+
+ bpr_size = 2 + (flash->size / SZ_64K / 8);
+
+ cmd = SST26_CMD_READ_BPR;
+ ret = spi_flash_read_common(flash, &cmd, 1, bpr_buff, bpr_size);
+ if (ret < 0) {
+ printf("SF: fail to read block-protection register\n");
+ return ret;
+ }
+
+ rptr_64k = min_t(u32, ofs + len , flash->size - SST26_BOUND_REG_SIZE);
+ lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE);
+
+ upper_64k = ((ofs + len) > (flash->size - SST26_BOUND_REG_SIZE));
+ lower_64k = (ofs < SST26_BOUND_REG_SIZE);
+
+ /* Lower bits in block-protection register are about 64k region */
+ bpr_ptr = lptr_64k / SZ_64K - 1;
+
+ /* Process 64K blocks region */
+ while (lptr_64k < rptr_64k) {
+ if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
+ return EACCES;
+
+ bpr_ptr++;
+ lptr_64k += SZ_64K;
+ }
+
+ /* 32K and 8K region bits in BPR are after 64k region bits */
+ bpr_ptr = (flash->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K;
+
+ /* Process lower 32K block region */
+ if (lower_64k)
+ if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
+ return EACCES;
+
+ bpr_ptr++;
+
+ /* Process upper 32K block region */
+ if (upper_64k)
+ if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
+ return EACCES;
+
+ bpr_ptr++;
+
+ /* Process lower 8K block regions */
+ for (i = 0; i < SST26_BPR_8K_NUM; i++) {
+ if (lower_64k)
+ if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
+ return EACCES;
+
+ /* In 8K area BPR has both read and write protection bits */
+ bpr_ptr += 2;
+ }
+
+ /* Process upper 8K block regions */
+ for (i = 0; i < SST26_BPR_8K_NUM; i++) {
+ if (upper_64k)
+ if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
+ return EACCES;
+
+ /* In 8K area BPR has both read and write protection bits */
+ bpr_ptr += 2;
+ }
+
+ /* If we check region status we don't need to write BPR back */
+ if (ctl == SST26_CTL_CHECK)
+ return 0;
+
+ cmd = SST26_CMD_WRITE_BPR;
+ ret = spi_flash_write_common(flash, &cmd, 1, bpr_buff, bpr_size);
+ if (ret < 0) {
+ printf("SF: fail to write block-protection register\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int sst26_unlock(struct spi_flash *flash, u32 ofs, size_t len)
+{
+ return sst26_lock_ctl(flash, ofs, len, SST26_CTL_UNLOCK);
+}
+
+static int sst26_lock(struct spi_flash *flash, u32 ofs, size_t len)
+{
+ return sst26_lock_ctl(flash, ofs, len, SST26_CTL_LOCK);
+}
+
+/*
+ * Returns EACCES (positive value) if region is locked, 0 if region is unlocked,
+ * and negative on errors.
+ */
+static int sst26_is_locked(struct spi_flash *flash, u32 ofs, size_t len)
+{
+ /*
+ * is_locked function is used for check before reading or erasing flash
+ * region, so offset and length might be not 64k allighned, so adjust
+ * them to be 64k allighned as sst26_lock_ctl works only with 64k
+ * allighned regions.
+ */
+ ofs -= ofs & (SZ_64K - 1);
+ len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len;
+
+ return sst26_lock_ctl(flash, ofs, len, SST26_CTL_CHECK);
+}
+
static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
{
struct spi_slave *spi = flash->spi;
if (ret)
return ret;
- return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+ return spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT);
}
int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
break;
}
- ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+ ret = spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT);
if (ret)
break;
#if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs,
- u32 *len)
+ u64 *len)
{
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
int shift = ffs(mask) - 1;
/*
* Return 1 if the entire region is locked, 0 otherwise
*/
-static int stm_is_locked_sr(struct spi_flash *flash, u32 ofs, u32 len,
+static int stm_is_locked_sr(struct spi_flash *flash, loff_t ofs, u64 len,
u8 sr)
{
loff_t lock_offs;
- u32 lock_len;
+ u64 lock_len;
stm_get_locked_range(flash, sr, &lock_offs, &lock_len);
}
#endif
-#ifdef CONFIG_SPI_FLASH_STMICRO
-static int micron_quad_enable(struct spi_flash *flash)
+static const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash)
{
- u8 qeb_status;
- int ret;
-
- ret = read_evcr(flash, &qeb_status);
- if (ret < 0)
- return ret;
-
- if (!(qeb_status & STATUS_QEB_MICRON))
- return 0;
-
- ret = write_evcr(flash, qeb_status & ~STATUS_QEB_MICRON);
- if (ret < 0)
- return ret;
+ int tmp;
+ u8 id[SPI_FLASH_MAX_ID_LEN];
+ const struct spi_flash_info *info;
+
+ tmp = spi_flash_cmd(flash->spi, CMD_READ_ID, id, SPI_FLASH_MAX_ID_LEN);
+ if (tmp < 0) {
+ printf("SF: error %d reading JEDEC ID\n", tmp);
+ return ERR_PTR(tmp);
+ }
- /* read EVCR and check it */
- ret = read_evcr(flash, &qeb_status);
- if (!(ret >= 0 && !(qeb_status & STATUS_QEB_MICRON))) {
- printf("SF: Micron EVCR Quad bit not clear\n");
- return -EINVAL;
+ info = spi_flash_ids;
+ for (; info->name != NULL; info++) {
+ if (info->id_len) {
+ if (!memcmp(info->id, id, info->id_len))
+ return info;
+ }
}
- return ret;
+ printf("SF: unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
+ id[0], id[1], id[2]);
+ return ERR_PTR(-ENODEV);
}
-#endif
-static int set_quad_mode(struct spi_flash *flash, u8 idcode0)
+static int set_quad_mode(struct spi_flash *flash,
+ const struct spi_flash_info *info)
{
- switch (idcode0) {
+ switch (JEDEC_MFR(info)) {
#ifdef CONFIG_SPI_FLASH_MACRONIX
case SPI_FLASH_CFI_MFR_MACRONIX:
return macronix_quad_enable(flash);
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO
case SPI_FLASH_CFI_MFR_STMICRO:
- return micron_quad_enable(flash);
+ debug("SF: QEB is volatile for %02x flash\n", JEDEC_MFR(info));
+ return 0;
#endif
default:
- printf("SF: Need set QEB func for %02x flash\n", idcode0);
+ printf("SF: Need set QEB func for %02x flash\n",
+ JEDEC_MFR(info));
return -1;
}
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
-int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
+int spi_flash_decode_fdt(struct spi_flash *flash)
{
+#ifdef CONFIG_DM_SPI_FLASH
fdt_addr_t addr;
fdt_size_t size;
- int node;
-
- /* If there is no node, do nothing */
- node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH);
- if (node < 0)
- return 0;
- addr = fdtdec_get_addr_size(blob, node, "memory-map", &size);
+ addr = dev_read_addr_size(flash->dev, "memory-map", &size);
if (addr == FDT_ADDR_T_NONE) {
debug("%s: Cannot decode address\n", __func__);
return 0;
}
- if (flash->size != size) {
+ if (flash->size > size) {
debug("%s: Memory map must cover entire device\n", __func__);
return -1;
}
flash->memory_map = map_sysmem(addr, size);
+#endif
return 0;
}
int spi_flash_scan(struct spi_flash *flash)
{
struct spi_slave *spi = flash->spi;
- const struct spi_flash_params *params;
- u16 jedec, ext_jedec;
- u8 cmd, idcode[5];
+ const struct spi_flash_info *info = NULL;
int ret;
- static u8 spi_read_cmds_array[] = {
- CMD_READ_ARRAY_SLOW,
- CMD_READ_ARRAY_FAST,
- CMD_READ_DUAL_OUTPUT_FAST,
- CMD_READ_QUAD_OUTPUT_FAST,
- CMD_READ_DUAL_IO_FAST,
- CMD_READ_QUAD_IO_FAST };
-
- /* Read the ID codes */
- ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
- if (ret) {
- printf("SF: Failed to get idcodes\n");
- return -EINVAL;
- }
-#ifdef DEBUG
- printf("SF: Got idcodes\n");
- print_buffer(0, idcode, 1, sizeof(idcode), 0);
-#endif
+ info = spi_flash_read_id(flash);
+ if (IS_ERR_OR_NULL(info))
+ return -ENOENT;
- jedec = idcode[1] << 8 | idcode[2];
- ext_jedec = idcode[3] << 8 | idcode[4];
-
- /* Validate params from spi_flash_params table */
- params = spi_flash_params_table;
- for (; params->name != NULL; params++) {
- if ((params->jedec >> 16) == idcode[0]) {
- if ((params->jedec & 0xFFFF) == jedec) {
- if (params->ext_jedec == 0)
- break;
- else if (params->ext_jedec == ext_jedec)
- break;
- }
+ /*
+ * Flash powers up read-only, so clear BP# bits.
+ *
+ * Note on some flash (like Macronix), QE (quad enable) bit is in the
+ * same status register as BP# bits, and we need preserve its original
+ * value during a reboot cycle as this is required by some platforms
+ * (like Intel ICH SPI controller working under descriptor mode).
+ */
+ if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL ||
+ (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) ||
+ (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX)) {
+ u8 sr = 0;
+
+ if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) {
+ read_sr(flash, &sr);
+ sr &= STATUS_QEB_MXIC;
}
+ write_sr(flash, sr);
}
- if (!params->name) {
- printf("SF: Unsupported flash IDs: ");
- printf("manuf %02x, jedec %04x, ext_jedec %04x\n",
- idcode[0], jedec, ext_jedec);
- return -EPROTONOSUPPORT;
- }
-
- /* Flash powers up read-only, so clear BP# bits */
- if (idcode[0] == SPI_FLASH_CFI_MFR_ATMEL ||
- idcode[0] == SPI_FLASH_CFI_MFR_MACRONIX ||
- idcode[0] == SPI_FLASH_CFI_MFR_SST)
- write_sr(flash, 0);
-
- /* Assign spi data */
- flash->name = params->name;
+ flash->name = info->name;
flash->memory_map = spi->memory_map;
- flash->dual_flash = spi->option;
- /* Assign spi flash flags */
- if (params->flags & SST_WR)
+ if (info->flags & SST_WR)
flash->flags |= SNOR_F_SST_WR;
- /* Assign spi_flash ops */
#ifndef CONFIG_DM_SPI_FLASH
flash->write = spi_flash_cmd_write_ops;
#if defined(CONFIG_SPI_FLASH_SST)
flash->read = spi_flash_cmd_read_ops;
#endif
- /* lock hooks are flash specific - assign them based on idcode0 */
- switch (idcode[0]) {
#if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
- case SPI_FLASH_CFI_MFR_STMICRO:
- case SPI_FLASH_CFI_MFR_SST:
+ /* NOR protection support for STmicro/Micron chips and similar */
+ if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_STMICRO ||
+ JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) {
flash->flash_lock = stm_lock;
flash->flash_unlock = stm_unlock;
flash->flash_is_locked = stm_is_locked;
+ }
#endif
- break;
- default:
- debug("SF: Lock ops not supported for %02x flash\n", idcode[0]);
+
+/* sst26wf series block protection implementation differs from other series */
+#if defined(CONFIG_SPI_FLASH_SST)
+ if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST && info->id[1] == 0x26) {
+ flash->flash_lock = sst26_lock;
+ flash->flash_unlock = sst26_unlock;
+ flash->flash_is_locked = sst26_is_locked;
}
+#endif
/* Compute the flash size */
flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
+ flash->page_size = info->page_size;
/*
* The Spansion S25FL032P and S25FL064P have 256b pages, yet use the
* 0x4d00 Extended JEDEC code. The rest of the Spansion flashes with
* the 0x4d00 Extended JEDEC code have 512b pages. All of the others
* have 256b pages.
*/
- if (ext_jedec == 0x4d00) {
- if ((jedec == 0x0215) || (jedec == 0x216))
- flash->page_size = 256;
- else
+ if (JEDEC_EXT(info) == 0x4d00) {
+ if ((JEDEC_ID(info) != 0x0215) &&
+ (JEDEC_ID(info) != 0x0216))
flash->page_size = 512;
- } else {
- flash->page_size = 256;
}
flash->page_size <<= flash->shift;
- flash->sector_size = params->sector_size << flash->shift;
- flash->size = flash->sector_size * params->nr_sectors << flash->shift;
+ flash->sector_size = info->sector_size << flash->shift;
+ flash->size = flash->sector_size * info->n_sectors << flash->shift;
#ifdef CONFIG_SF_DUAL_FLASH
if (flash->dual_flash & SF_DUAL_STACKED_FLASH)
flash->size <<= 1;
#endif
+#ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
/* Compute erase sector and command */
- if (params->flags & SECT_4K) {
+ if (info->flags & SECT_4K) {
flash->erase_cmd = CMD_ERASE_4K;
flash->erase_size = 4096 << flash->shift;
- } else if (params->flags & SECT_32K) {
- flash->erase_cmd = CMD_ERASE_32K;
- flash->erase_size = 32768 << flash->shift;
- } else {
+ } else
+#endif
+ {
flash->erase_cmd = CMD_ERASE_64K;
flash->erase_size = flash->sector_size;
}
/* Now erase size becomes valid sector size */
flash->sector_size = flash->erase_size;
- /* Look for the fastest read cmd */
- cmd = fls(params->e_rd_cmd & spi->mode_rx);
- if (cmd) {
- cmd = spi_read_cmds_array[cmd - 1];
- flash->read_cmd = cmd;
- } else {
- /* Go for default supported read cmd */
- flash->read_cmd = CMD_READ_ARRAY_FAST;
- }
-
- /* Not require to look for fastest only two write cmds yet */
- if (params->flags & WR_QPP && spi->mode & SPI_TX_QUAD)
+ /* Look for read commands */
+ flash->read_cmd = CMD_READ_ARRAY_FAST;
+ if (spi->mode & SPI_RX_SLOW)
+ flash->read_cmd = CMD_READ_ARRAY_SLOW;
+ else if (spi->mode & SPI_RX_QUAD && info->flags & RD_QUAD)
+ flash->read_cmd = CMD_READ_QUAD_OUTPUT_FAST;
+ else if (spi->mode & SPI_RX_DUAL && info->flags & RD_DUAL)
+ flash->read_cmd = CMD_READ_DUAL_OUTPUT_FAST;
+
+ /* Look for write commands */
+ if (info->flags & WR_QPP && spi->mode & SPI_TX_QUAD)
flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
else
/* Go for default supported write cmd */
if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
(flash->read_cmd == CMD_READ_QUAD_IO_FAST) ||
(flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
- ret = set_quad_mode(flash, idcode[0]);
+ ret = set_quad_mode(flash, info);
if (ret) {
- debug("SF: Fail to set QEB for %02x\n", idcode[0]);
+ debug("SF: Fail to set QEB for %02x\n",
+ JEDEC_MFR(info));
return -EINVAL;
}
}
}
#ifdef CONFIG_SPI_FLASH_STMICRO
- if (params->flags & E_FSR)
+ if (info->flags & E_FSR)
flash->flags |= SNOR_F_USE_FSR;
#endif
/* Configure the BAR - discover bank cmds and read current bank */
#ifdef CONFIG_SPI_FLASH_BAR
- ret = spi_flash_read_bar(flash, idcode[0]);
+ ret = read_bar(flash, info);
if (ret < 0)
return ret;
#endif
-#if CONFIG_IS_ENABLED(OF_CONTROL)
- ret = spi_flash_decode_fdt(gd->fdt_blob, flash);
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+ ret = spi_flash_decode_fdt(flash);
if (ret) {
debug("SF: FDT decode error\n");
return -EINVAL;
}
#endif
- return ret;
+ return 0;
}
projects / u-boot / blobdiff