sf: Read flash bank addr register at probe time

[u-boot] / drivers / mtd / spi / spi_flash.c

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index de6fd58e8c30831fb1439222e42b0bb2e1c7f872..64b57ecc7103f4ce07d056bceb6e4e198a1d2c6a 100644 (file)
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -124,9 +124,6 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset,
                }
        }
 
-       debug("SF: program %s %zu bytes @ %#x\n",
-             ret ? "failure" : "success", len, offset);
-
        spi_release_bus(flash->spi);
        return ret;
 }
@@ -281,6 +278,75 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
        return 0;
 }
 
+int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
+{
+       u8 cmd;
+       int ret;
+
+       if (flash->bank_curr == bank_sel) {
+               debug("SF: not require to enable bank%d\n", bank_sel);
+               return 0;
+       }
+
+       cmd = flash->bank_write_cmd;
+       ret = spi_flash_cmd_write_enable(flash);
+       if (ret < 0) {
+               debug("SF: enabling write failed\n");
+               return ret;
+       }
+
+       ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &bank_sel, 1);
+       if (ret) {
+               debug("SF: fail to write bank addr register\n");
+               return ret;
+       }
+       flash->bank_curr = bank_sel;
+
+       ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+       if (ret < 0) {
+               debug("SF: write bank addr register timed out\n");
+               return ret;
+       }
+
+       return 0;
+}
+
+int spi_flash_bank_config(struct spi_flash *flash, u8 idcode0)
+{
+       u8 cmd;
+       u8 curr_bank = 0;
+
+       /* discover bank cmds */
+       switch (idcode0) {
+       case SPI_FLASH_SPANSION_IDCODE0:
+               flash->bank_read_cmd = CMD_BANKADDR_BRRD;
+               flash->bank_write_cmd = CMD_BANKADDR_BRWR;
+               break;
+       case SPI_FLASH_STMICRO_IDCODE0:
+       case SPI_FLASH_WINBOND_IDCODE0:
+               flash->bank_read_cmd = CMD_EXTNADDR_RDEAR;
+               flash->bank_write_cmd = CMD_EXTNADDR_WREAR;
+               break;
+       default:
+               printf("SF: Unsupported bank commands %02x\n", idcode0);
+               return -1;
+       }
+
+       /* read the bank reg - on which bank the flash is in currently */
+       cmd = flash->bank_read_cmd;
+       if (flash->size > SPI_FLASH_16MB_BOUN) {
+               if (spi_flash_read_common(flash, &cmd, 1, &curr_bank, 1)) {
+                       debug("SF: fail to read bank addr register\n");
+                       return -1;
+               }
+               flash->bank_curr = curr_bank;
+       } else {
+               flash->bank_curr = curr_bank;
+       }
+
+       return 0;
+}
+
 #ifdef CONFIG_OF_CONTROL
 int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
 {
@@ -425,6 +491,11 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
                goto err_manufacturer_probe;
        }
 
+       /* Configure the BAR - disover bank cmds and read current bank  */
+       ret = spi_flash_bank_config(flash, *idp);
+       if (ret < 0)
+               goto err_manufacturer_probe;
+
 #ifdef CONFIG_OF_CONTROL
        if (spi_flash_decode_fdt(gd->fdt_blob, flash)) {
                debug("SF: FDT decode error\n");