sf: Discover the bank addr commands

[u-boot] / drivers / mtd / spi / spi_flash.c

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 6fa932cbd9c3de70300a136e13136932e7ad49c1..7e19953b0a478aeb798b413e1d20fb83fd41cd0b 100644 (file)
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -124,9 +124,6 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset,
                }
        }
 
-       debug("SF: program %s %zu bytes @ %#x\n",
-             ret ? "failure" : "success", len, offset);
-
        spi_release_bus(flash->spi);
        return ret;
 }
@@ -207,7 +204,7 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
 
 int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len)
 {
-       u32 start, end, erase_size;
+       u32 end, erase_size;
        int ret;
        u8 cmd[4];
 
@@ -227,8 +224,7 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len)
                cmd[0] = CMD_ERASE_4K;
        else
                cmd[0] = CMD_ERASE_64K;
-       start = offset;
-       end = start + len;
+       end = offset + len;
 
        while (offset < end) {
                spi_flash_addr(offset, cmd);
@@ -250,8 +246,6 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len)
                        goto out;
        }
 
-       debug("SF: Successfully erased %zu bytes @ %#x\n", len, start);
-
  out:
        spi_release_bus(flash->spi);
        return ret;
@@ -284,6 +278,53 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
        return 0;
 }
 
+int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
+{
+       u8 cmd;
+       int ret;
+
+       ret = spi_flash_cmd_write_enable(flash);
+       if (ret < 0) {
+               debug("SF: enabling write failed\n");
+               return ret;
+       }
+
+       ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &bank_sel, 1);
+       if (ret) {
+               debug("SF: fail to write bank addr register\n");
+               return ret;
+       }
+
+       ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+       if (ret < 0) {
+               debug("SF: write bank addr register timed out\n");
+               return ret;
+       }
+
+       return 0;
+}
+
+int spi_flash_bank_config(struct spi_flash *flash, u8 idcode0)
+{
+       /* discover bank cmds */
+       switch (idcode0) {
+       case SPI_FLASH_SPANSION_IDCODE0:
+               flash->bank_read_cmd = CMD_BANKADDR_BRRD;
+               flash->bank_write_cmd = CMD_BANKADDR_BRWR;
+               break;
+       case SPI_FLASH_STMICRO_IDCODE0:
+       case SPI_FLASH_WINBOND_IDCODE0:
+               flash->bank_read_cmd = CMD_EXTNADDR_RDEAR;
+               flash->bank_write_cmd = CMD_EXTNADDR_WREAR;
+               break;
+       default:
+               printf("SF: Unsupported bank commands %02x\n", idcode0);
+               return -1;
+       }
+
+       return 0;
+}
+
 #ifdef CONFIG_OF_CONTROL
 int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
 {