Merge git://git.denx.de/u-boot-marvell

[u-boot] / drivers / net / altera_tse.h

diff --git a/drivers/net/altera_tse.h b/drivers/net/altera_tse.h
index 471a88013828720b5a8078f29add5bb26bd8c754..2b1af8142978d6526989838d5dd50e85d5f93150 100644 (file)
--- a/drivers/net/altera_tse.h
+++ b/drivers/net/altera_tse.h
@@ -13,6 +13,10 @@
 
 #define __packed_1_    __packed __aligned(1)
 
+/* dma type */
+#define ALT_SGDMA      0
+#define ALT_MSGDMA     1
+
 /* SGDMA Stuff */
 #define ALT_SGDMA_STATUS_BUSY_MSK                              BIT(4)
 
@@ -84,6 +88,64 @@ struct alt_sgdma_registers {
        u32 descriptor_pad[3];
 };
 
+/* mSGDMA Stuff */
+
+/* mSGDMA extended descriptor format */
+struct msgdma_extended_desc {
+       u32 read_addr_lo;       /* data buffer source address low bits */
+       u32 write_addr_lo;      /* data buffer destination address low bits */
+       u32 len;
+       u32 burst_seq_num;
+       u32 stride;
+       u32 read_addr_hi;       /* data buffer source address high bits */
+       u32 write_addr_hi;      /* data buffer destination address high bits */
+       u32 control;            /* characteristics of the transfer */
+};
+
+/* mSGDMA descriptor control field bit definitions */
+#define MSGDMA_DESC_CTL_GEN_SOP                BIT(8)
+#define MSGDMA_DESC_CTL_GEN_EOP                BIT(9)
+#define MSGDMA_DESC_CTL_END_ON_EOP     BIT(12)
+#define MSGDMA_DESC_CTL_END_ON_LEN     BIT(13)
+#define MSGDMA_DESC_CTL_GO             BIT(31)
+
+/* Tx buffer control flags */
+#define MSGDMA_DESC_CTL_TX_SINGLE      (MSGDMA_DESC_CTL_GEN_SOP |      \
+                                        MSGDMA_DESC_CTL_GEN_EOP |      \
+                                        MSGDMA_DESC_CTL_GO)
+
+#define MSGDMA_DESC_CTL_RX_SINGLE      (MSGDMA_DESC_CTL_END_ON_EOP |   \
+                                        MSGDMA_DESC_CTL_END_ON_LEN |   \
+                                        MSGDMA_DESC_CTL_GO)
+
+/* mSGDMA extended descriptor stride definitions */
+#define MSGDMA_DESC_TX_STRIDE          0x00010001
+#define MSGDMA_DESC_RX_STRIDE          0x00010001
+
+/* mSGDMA dispatcher control and status register map */
+struct msgdma_csr {
+       u32 status;             /* Read/Clear */
+       u32 control;            /* Read/Write */
+       u32 rw_fill_level;
+       u32 resp_fill_level;    /* bit 15:0 */
+       u32 rw_seq_num;
+       u32 pad[3];             /* reserved */
+};
+
+/* mSGDMA CSR status register bit definitions */
+#define MSGDMA_CSR_STAT_BUSY                   BIT(0)
+#define MSGDMA_CSR_STAT_RESETTING              BIT(6)
+#define MSGDMA_CSR_STAT_MASK                   0x3FF
+
+/* mSGDMA CSR control register bit definitions */
+#define MSGDMA_CSR_CTL_RESET                   BIT(1)
+
+/* mSGDMA response register map */
+struct msgdma_response {
+       u32 bytes_transferred;
+       u32 status;
+};
+
 /* TSE Stuff */
 #define ALTERA_TSE_CMD_TX_ENA_MSK              BIT(0)
 #define ALTERA_TSE_CMD_RX_ENA_MSK              BIT(1)
@@ -141,19 +203,29 @@ struct alt_tse_mac {
        u32 reserved3[0x38];
 };
 
+struct tse_ops {
+       int (*send)(struct udevice *dev, void *packet, int length);
+       int (*recv)(struct udevice *dev, int flags, uchar **packetp);
+       int (*free_pkt)(struct udevice *dev, uchar *packet, int length);
+       void (*stop)(struct udevice *dev);
+};
+
 struct altera_tse_priv {
        struct alt_tse_mac *mac_dev;
-       struct alt_sgdma_registers *sgdma_rx;
-       struct alt_sgdma_registers *sgdma_tx;
+       void *sgdma_rx;
+       void *sgdma_tx;
        unsigned int rx_fifo_depth;
        unsigned int tx_fifo_depth;
-       struct alt_sgdma_descriptor *rx_desc;
-       struct alt_sgdma_descriptor *tx_desc;
+       void *rx_desc;
+       void *tx_desc;
+       void *rx_resp;
        unsigned char *rx_buf;
        unsigned int phyaddr;
        unsigned int interface;
        struct phy_device *phydev;
        struct mii_dev *bus;
+       const struct tse_ops *ops;
+       int dma_type;
 };
 
 #endif /* _ALTERA_TSE_H_ */