/*
* (C) Copyright 2011
* eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ * Written-by: Ajay Bhargav <contact@8051projects.net>
*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Contributor: Mahavir Jain <mjain@marvell.com>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
return !timeout;
}
-static int smi_reg_read(const char *devname, u8 phy_addr, u8 phy_reg,
- u16 *value)
+static int smi_reg_read(struct mii_dev *bus, int phy_addr, int devad,
+ int phy_reg)
{
- struct eth_device *dev = eth_get_dev_by_name(devname);
+ u16 value = 0;
+ struct eth_device *dev = eth_get_dev_by_name(bus->name);
struct armdfec_device *darmdfec = to_darmdfec(dev);
struct armdfec_reg *regs = darmdfec->regs;
u32 val;
if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
val = readl(®s->phyadr);
- *value = val & 0x1f;
- return 0;
+ value = val & 0x1f;
+ return value;
}
/* check parameters */
}
/* wait for the SMI register to become available */
- if (armdfec_phy_timeout(®s->smi, SMI_BUSY, FALSE)) {
+ if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) {
printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
return -1;
}
writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_R, ®s->smi);
/* now wait for the data to be valid */
- if (armdfec_phy_timeout(®s->smi, SMI_R_VALID, TRUE)) {
+ if (armdfec_phy_timeout(®s->smi, SMI_R_VALID, true)) {
val = readl(®s->smi);
printf("ARMD100 FEC: (%s) PHY Read timeout, val=0x%x\n",
__func__, val);
return -1;
}
val = readl(®s->smi);
- *value = val & 0xffff;
+ value = val & 0xffff;
- return 0;
+ return value;
}
-static int smi_reg_write(const char *devname,
- u8 phy_addr, u8 phy_reg, u16 value)
+static int smi_reg_write(struct mii_dev *bus, int phy_addr, int devad,
+ int phy_reg, u16 value)
{
- struct eth_device *dev = eth_get_dev_by_name(devname);
+ struct eth_device *dev = eth_get_dev_by_name(bus->name);
struct armdfec_device *darmdfec = to_darmdfec(dev);
struct armdfec_reg *regs = darmdfec->regs;
}
/* wait for the SMI register to become available */
- if (armdfec_phy_timeout(®s->smi, SMI_BUSY, FALSE)) {
+ if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) {
printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
return -1;
}
struct armdfec_device *darmdfec = to_darmdfec(dev);
struct armdfec_reg *regs = darmdfec->regs;
int phy_adr;
+ u32 temp;
armdfec_init_rx_desc_ring(darmdfec);
update_hash_table_mac_address(darmdfec, NULL, dev->enetaddr);
/* Update TX and RX queue descriptor register */
- writel((u32)darmdfec->p_txdesc, ®s->txcdp[TXQ]);
- writel((u32)darmdfec->p_rxdesc, ®s->rxfdp[RXQ]);
- writel((u32)darmdfec->p_rxdesc_curr, ®s->rxcdp[RXQ]);
+ temp = (u32)®s->txcdp[TXQ];
+ writel((u32)darmdfec->p_txdesc, temp);
+ temp = (u32)®s->rxfdp[RXQ];
+ writel((u32)darmdfec->p_rxdesc, temp);
+ temp = (u32)®s->rxcdp[RXQ];
+ writel((u32)darmdfec->p_rxdesc_curr, temp);
/* Enable Interrupts */
writel(ALL_INTS, ®s->im);
clrbits_le32(®s->pconf, PCR_EN);
}
-static int armdfec_send(struct eth_device *dev, volatile void *dataptr,
- int datasize)
+static int armdfec_send(struct eth_device *dev, void *dataptr, int datasize)
{
struct armdfec_device *darmdfec = to_darmdfec(dev);
struct armdfec_reg *regs = darmdfec->regs;
struct tx_desc *p_txdesc = darmdfec->p_txdesc;
void *p = (void *)dataptr;
int retry = PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS;
- u32 cmd_sts;
+ u32 cmd_sts, temp;
/* Copy buffer if it's misaligned */
if ((u32)dataptr & 0x07) {
p_txdesc->byte_cnt = datasize;
/* Apply send command using high priority TX queue */
- writel((u32)p_txdesc, ®s->txcdp[TXQ]);
+ temp = (u32)®s->txcdp[TXQ];
+ writel((u32)p_txdesc, temp);
writel(SDMA_CMD_TXDL | SDMA_CMD_TXDH | SDMA_CMD_ERD, ®s->sdma_cmd);
/*
struct rx_desc *p_rxdesc_curr = darmdfec->p_rxdesc_curr;
u32 cmd_sts;
u32 timeout = 0;
+ u32 temp;
/* wait untill rx packet available or timeout */
do {
} else {
/* !!! call higher layer processing */
debug("ARMD100 FEC: (%s) Sending Received packet to"
- " upper layer (NetReceive)\n", __func__);
+ " upper layer (net_process_received_packet)\n", __func__);
/*
* let the upper layer handle the packet, subtract offset
* as two dummy bytes are added in received buffer see
* PORT_CONFIG_EXT register bit TWO_Byte_Stuff_Mode bit.
*/
- NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET),
- (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
+ net_process_received_packet(
+ p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET,
+ (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
}
/*
* free these descriptors and point next in the ring
p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
p_rxdesc_curr->byte_cnt = 0;
- writel((u32)p_rxdesc_curr->nxtdesc_p, (u32)&darmdfec->p_rxdesc_curr);
+ temp = (u32)&darmdfec->p_rxdesc_curr;
+ writel((u32)p_rxdesc_curr->nxtdesc_p, temp);
return 0;
}
/* Assign ARMADA100 Fast Ethernet Controller Base Address */
darmdfec->regs = (void *)base_addr;
- /* must be less than NAMESIZE (16) */
+ /* must be less than sizeof(dev->name) */
strcpy(dev->name, "armd-fec0");
dev->init = armdfec_init;
eth_register(dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
- miiphy_register(dev->name, smi_reg_read, smi_reg_write);
+ int retval;
+ struct mii_dev *mdiodev = mdio_alloc();
+ if (!mdiodev)
+ return -ENOMEM;
+ strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+ mdiodev->read = smi_reg_read;
+ mdiodev->write = smi_reg_write;
+
+ retval = mdio_register(mdiodev);
+ if (retval < 0)
+ return retval;
#endif
return 0;
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