dwc2 USB controller hangs with lan78xx

[u-boot] / drivers / net / designware.c

diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 6d5307128d866ca23f9e9fbbc0f8945aa12f0460..10a87096b72c4a1a02a62f09a1298cb393329ca5 100644 (file)
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2010
  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /*
@@ -23,8 +22,6 @@
 #include <power/regulator.h>
 #include "designware.h"
 
-DECLARE_GLOBAL_DATA_PTR;
-
 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 {
 #ifdef CONFIG_DM_ETH
@@ -283,6 +280,15 @@ int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
 
        writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
 
+       /*
+        * When a MII PHY is used, we must set the PS bit for the DMA
+        * reset to succeed.
+        */
+       if (priv->phydev->interface == PHY_INTERFACE_MODE_MII)
+               writel(readl(&mac_p->conf) | MII_PORTSELECT, &mac_p->conf);
+       else
+               writel(readl(&mac_p->conf) & ~MII_PORTSELECT, &mac_p->conf);
+
        start = get_timer(0);
        while (readl(&dma_p->busmode) & DMAMAC_SRST) {
                if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
@@ -684,7 +690,7 @@ int designware_eth_probe(struct udevice *dev)
                                break;
 
                        err = clk_enable(&priv->clocks[i]);
-                       if (err) {
+                       if (err && err != -ENOSYS && err != -ENOTSUPP) {
                                pr_err("failed to enable clock %d\n", i);
                                clk_free(&priv->clocks[i]);
                                goto clk_err;