u32 status; /* 0x14 */
u32 opmode; /* 0x18 */
u32 intenable; /* 0x1c */
- u8 reserved[40];
+ u32 reserved1[2];
+ u32 axibus; /* 0x28 */
+ u32 reserved2[7];
u32 currhosttxdesc; /* 0x48 */
u32 currhostrxdesc; /* 0x4c */
u32 currhosttxbuffaddr; /* 0x50 */
char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
u32 interface;
+ u32 max_speed;
u32 tx_currdescnum;
u32 rx_currdescnum;
struct eth_mac_regs *mac_regs_p;
struct eth_dma_regs *dma_regs_p;
-
+#ifndef CONFIG_DM_ETH
struct eth_device *dev;
+#endif
struct phy_device *phydev;
struct mii_dev *bus;
};