#define TOUT_LOOP 100000
-#undef virt_to_bus
-#define virt_to_bus(x) ((unsigned long)x)
+#define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
#define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
#define mdelay(n) udelay((n)*1000)
-#define E1000_DEFAULT_PBA 0x000a0026
+#define E1000_DEFAULT_PCI_PBA 0x00000030
+#define E1000_DEFAULT_PCIE_PBA 0x000a0026
/* NIC specific static variables go here */
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
static int e1000_phy_reset(struct e1000_hw *hw);
static int e1000_detect_gig_phy(struct e1000_hw *hw);
-static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
- uint16_t words,
- uint16_t *data);
static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
static void e1000_set_media_type(struct e1000_hw *hw);
#define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
#ifndef CONFIG_AP1000 /* remove for warnings */
+static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
+ uint16_t words,
+ uint16_t *data);
/******************************************************************************
* Raises the EEPROM's clock input.
*
struct e1000_eeprom_info *eeprom = &hw->eeprom;
uint32_t eecd, i = 0;
- DEBUGOUT();
+ DEBUGFUNC();
if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
return -E1000_ERR_SWFW_SYNC;
int32_t ret_val = E1000_SUCCESS;
uint16_t eeprom_size;
- DEBUGOUT();
+ DEBUGFUNC();
switch (hw->mac_type) {
case e1000_82542_rev2_0:
return -E1000_ERR_EEPROM;
}
}
+
+/*****************************************************************************
+ * Set PHY to class A mode
+ * Assumes the following operations will follow to enable the new class mode.
+ * 1. Do a PHY soft reset
+ * 2. Restart auto-negotiation or force link.
+ *
+ * hw - Struct containing variables accessed by shared code
+ ****************************************************************************/
+static int32_t
+e1000_set_phy_mode(struct e1000_hw *hw)
+{
+ int32_t ret_val;
+ uint16_t eeprom_data;
+
+ DEBUGFUNC();
+
+ if ((hw->mac_type == e1000_82545_rev_3) &&
+ (hw->media_type == e1000_media_type_copper)) {
+ ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
+ 1, &eeprom_data);
+ if (ret_val)
+ return ret_val;
+
+ if ((eeprom_data != EEPROM_RESERVED_WORD) &&
+ (eeprom_data & EEPROM_PHY_CLASS_A)) {
+ ret_val = e1000_write_phy_reg(hw,
+ M88E1000_PHY_PAGE_SELECT, 0x000B);
+ if (ret_val)
+ return ret_val;
+ ret_val = e1000_write_phy_reg(hw,
+ M88E1000_PHY_GEN_CONTROL, 0x8104);
+ if (ret_val)
+ return ret_val;
+
+ hw->phy_reset_disable = FALSE;
+ }
+ }
+
+ return E1000_SUCCESS;
+}
#endif /* #ifndef CONFIG_AP1000 */
/***************************************************************************
uint32_t ctrl_ext;
uint32_t icr;
uint32_t manc;
+ uint32_t pba = 0;
DEBUGFUNC();
+ /* get the correct pba value for both PCI and PCIe*/
+ if (hw->mac_type < e1000_82571)
+ pba = E1000_DEFAULT_PCI_PBA;
+ else
+ pba = E1000_DEFAULT_PCIE_PBA;
+
/* For 82542 (rev 2.0), disable MWI before issuing a device reset */
if (hw->mac_type == e1000_82542_rev2_0) {
DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
if (hw->mac_type == e1000_82542_rev2_0) {
pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
}
- E1000_WRITE_REG(hw, PBA, E1000_DEFAULT_PBA);
+ E1000_WRITE_REG(hw, PBA, pba);
}
/******************************************************************************
return 0;
}
-/*****************************************************************************
- * Set PHY to class A mode
- * Assumes the following operations will follow to enable the new class mode.
- * 1. Do a PHY soft reset
- * 2. Restart auto-negotiation or force link.
- *
- * hw - Struct containing variables accessed by shared code
- ****************************************************************************/
-static int32_t
-e1000_set_phy_mode(struct e1000_hw *hw)
-{
- int32_t ret_val;
- uint16_t eeprom_data;
-
- DEBUGFUNC();
-
- if ((hw->mac_type == e1000_82545_rev_3) &&
- (hw->media_type == e1000_media_type_copper)) {
- ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
- 1, &eeprom_data);
- if (ret_val)
- return ret_val;
-
- if ((eeprom_data != EEPROM_RESERVED_WORD) &&
- (eeprom_data & EEPROM_PHY_CLASS_A)) {
- ret_val = e1000_write_phy_reg(hw,
- M88E1000_PHY_PAGE_SELECT, 0x000B);
- if (ret_val)
- return ret_val;
- ret_val = e1000_write_phy_reg(hw,
- M88E1000_PHY_GEN_CONTROL, 0x8104);
- if (ret_val)
- return ret_val;
-
- hw->phy_reset_disable = FALSE;
- }
- }
-
- return E1000_SUCCESS;
-}
-
/******************************************************************************
* Make sure we have a valid PHY and change PHY mode before link setup.
*
int32_t ret_val;
uint16_t phy_data;
- DEBUGOUT();
+ DEBUGFUNC();
if (hw->phy_reset_disable)
return E1000_SUCCESS;
txp = tx_base + tx_tail;
tx_tail = (tx_tail + 1) % 8;
- txp->buffer_addr = cpu_to_le64(virt_to_bus(packet));
+ txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, packet));
txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
txp->upper.data = 0;
E1000_WRITE_REG(hw, TDT, tx_tail);
int idx = 0;
u32 PciCommandWord;
+ DEBUGFUNC();
+
while (1) { /* Find PCI device(s) */
if ((devno = pci_find_devices(supported, idx++)) < 0) {
break;
hw = (struct e1000_hw *) malloc(sizeof (*hw));
hw->pdev = devno;
nic->priv = hw;
- nic->iobase = bus_to_phys(devno, iobase);
sprintf(nic->name, "e1000#%d", card_number);
hw->autoneg_failed = 0;
hw->autoneg = 1;
hw->get_link_status = TRUE;
- hw->hw_addr = (typeof(hw->hw_addr)) iobase;
+ hw->hw_addr =
+ pci_map_bar(devno, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
hw->mac_type = e1000_undefined;
/* MAC and Phy settings */
projects / u-boot / blobdiff