pci: Set PCI_COMMAND_IO bit for VGA device

[u-boot] / drivers / net / e1000.c

diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 412ed1450d2a59cd03c69407a4b66ddc556bebaa..2ba03ed73e45e40b177221cc47483465dba7a3cc 100644 (file)
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -32,6 +32,7 @@ tested on both gig copper and gig fiber boards
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
+#include <memalign.h>
 #include <pci.h>
 #include "e1000.h"
 
@@ -1221,13 +1222,6 @@ e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6])
        if (e1000_is_second_port(hw))
                enetaddr[5] ^= 1;
 
-#ifdef CONFIG_E1000_FALLBACK_MAC
-       if (!is_valid_ethaddr(nic->enetaddr)) {
-               unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC;
-
-               memcpy(enetaddr, fb_mac, NODE_ADDRESS_SIZE);
-       }
-#endif
        return 0;
 }
 #endif
@@ -4985,8 +4979,8 @@ e1000_configure_tx(struct e1000_hw *hw)
        unsigned long tipg, tarc;
        uint32_t ipgr1, ipgr2;
 
-       E1000_WRITE_REG(hw, TDBAL, (unsigned long)tx_base & 0xffffffff);
-       E1000_WRITE_REG(hw, TDBAH, (unsigned long)tx_base >> 32);
+       E1000_WRITE_REG(hw, TDBAL, lower_32_bits((unsigned long)tx_base));
+       E1000_WRITE_REG(hw, TDBAH, upper_32_bits((unsigned long)tx_base));
 
        E1000_WRITE_REG(hw, TDLEN, 128);
 
@@ -5110,6 +5104,7 @@ e1000_configure_rx(struct e1000_hw *hw)
 {
        unsigned long rctl, ctrl_ext;
        rx_tail = 0;
+
        /* make sure receives are disabled while setting up the descriptors */
        rctl = E1000_READ_REG(hw, RCTL);
        E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
@@ -5129,8 +5124,8 @@ e1000_configure_rx(struct e1000_hw *hw)
                E1000_WRITE_FLUSH(hw);
        }
        /* Setup the Base and Length of the Rx Descriptor Ring */
-       E1000_WRITE_REG(hw, RDBAL, (unsigned long)rx_base & 0xffffffff);
-       E1000_WRITE_REG(hw, RDBAH, (unsigned long)rx_base >> 32);
+       E1000_WRITE_REG(hw, RDBAL, lower_32_bits((unsigned long)rx_base));
+       E1000_WRITE_REG(hw, RDBAH, upper_32_bits((unsigned long)rx_base));
 
        E1000_WRITE_REG(hw, RDLEN, 128);