DEBUGFUNC();
- swsm = E1000_READ_REG(hw, SWSM);
- swsm &= ~E1000_SWSM_SMBI;
- E1000_WRITE_REG(hw, SWSM, swsm);
-
if (hw->mac_type != e1000_80003es2lan)
return E1000_SUCCESS;
if (e1000_get_hw_eeprom_semaphore(hw))
return -E1000_ERR_SWFW_SYNC;
- if (hw->mac_type == e1000_igb)
- swfw_sync = E1000_READ_REG(hw, I210_SW_FW_SYNC);
- else
- swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
+ swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
if (!(swfw_sync & (fwmask | swmask)))
break;
if (hw->mac_type >= e1000_82571)
mdelay(10);
+
} else {
/* Read the Extended Device Control Register, assert the PHY_RESET_DIR
* bit to put the PHY into reset. Then, take it out of reset.