+// SPDX-License-Identifier: GPL-2.0
/*
* Opencore 10/100 ethernet mac driver
*
* Thierry Reding <thierry.reding@avionic-design.de>
* Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
* Copyright (C) 2016 Cadence Design Systems Inc.
- *
- * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
-#include <dm/device.h>
+#include <dm.h>
#include <dm/platform_data/net_ethoc.h>
#include <linux/io.h>
#include <malloc.h>
#include <net.h>
#include <miiphy.h>
#include <asm/cache.h>
+#include <wait_bit.h>
/* register offsets */
#define MODER 0x00
u32 num_rx;
u32 cur_rx;
void __iomem *iobase;
+ void __iomem *packet;
+ phys_addr_t packet_phys;
+
+#ifdef CONFIG_PHYLIB
+ struct mii_dev *bus;
+ struct phy_device *phydev;
+#endif
};
/**
u32 addr;
};
+static inline u32 *ethoc_reg(struct ethoc *priv, size_t offset)
+{
+ return priv->iobase + offset;
+}
+
static inline u32 ethoc_read(struct ethoc *priv, size_t offset)
{
- return readl(priv->iobase + offset);
+ return readl(ethoc_reg(priv, offset));
}
static inline void ethoc_write(struct ethoc *priv, size_t offset, u32 data)
{
- writel(data, priv->iobase + offset);
+ writel(data, ethoc_reg(priv, offset));
}
static inline void ethoc_read_bd(struct ethoc *priv, int index,
static int ethoc_init_ring(struct ethoc *priv)
{
struct ethoc_bd bd;
+ phys_addr_t addr = priv->packet_phys;
int i;
priv->cur_tx = 0;
bd.addr = 0;
for (i = 0; i < priv->num_tx; i++) {
+ if (addr) {
+ bd.addr = addr;
+ addr += PKTSIZE_ALIGN;
+ }
if (i == priv->num_tx - 1)
bd.stat |= TX_BD_WRAP;
bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
for (i = 0; i < priv->num_rx; i++) {
- bd.addr = virt_to_phys(net_rx_packets[i]);
+ if (addr) {
+ bd.addr = addr;
+ addr += PKTSIZE_ALIGN;
+ } else {
+ bd.addr = virt_to_phys(net_rx_packets[i]);
+ }
if (i == priv->num_rx - 1)
bd.stat |= RX_BD_WRAP;
static int ethoc_init_common(struct ethoc *priv)
{
+ int ret = 0;
+
priv->num_tx = 1;
priv->num_rx = PKTBUFSRX;
ethoc_write(priv, TX_BD_NUM, priv->num_tx);
ethoc_init_ring(priv);
ethoc_reset(priv);
- return 0;
+#ifdef CONFIG_PHYLIB
+ ret = phy_startup(priv->phydev);
+ if (ret) {
+ printf("Could not initialize PHY %s\n",
+ priv->phydev->dev->name);
+ return ret;
+ }
+#endif
+ return ret;
+}
+
+static void ethoc_stop_common(struct ethoc *priv)
+{
+ ethoc_disable_rx_and_tx(priv);
+#ifdef CONFIG_PHYLIB
+ phy_shutdown(priv->phydev);
+#endif
}
static int ethoc_update_rx_stats(struct ethoc_bd *bd)
int size = bd.stat >> 16;
size -= 4; /* strip the CRC */
- *packetp = net_rx_packets[i];
+ if (priv->packet)
+ *packetp = priv->packet + entry * PKTSIZE_ALIGN;
+ else
+ *packetp = net_rx_packets[i];
return size;
} else {
return 0;
bd.stat |= TX_BD_PAD;
else
bd.stat &= ~TX_BD_PAD;
- bd.addr = virt_to_phys(packet);
+ if (priv->packet) {
+ void *p = priv->packet + entry * PKTSIZE_ALIGN;
+
+ memcpy(p, packet, length);
+ packet = p;
+ } else {
+ bd.addr = virt_to_phys(packet);
+ }
flush_dcache_range((ulong)packet, (ulong)packet + length);
bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
bd.stat |= TX_BD_LEN(length);
struct ethoc_bd bd;
u32 i = priv->cur_rx % priv->num_rx;
u32 entry = priv->num_tx + i;
+ void *src;
ethoc_read_bd(priv, entry, &bd);
+ if (priv->packet)
+ src = priv->packet + entry * PKTSIZE_ALIGN;
+ else
+ src = net_rx_packets[i];
/* clear the buffer descriptor so it can be reused */
- flush_dcache_range((ulong)net_rx_packets[i],
- (ulong)net_rx_packets[i] + PKTSIZE_ALIGN);
+ flush_dcache_range((ulong)src,
+ (ulong)src + PKTSIZE_ALIGN);
bd.stat &= ~RX_BD_STATS;
bd.stat |= RX_BD_EMPTY;
ethoc_write_bd(priv, entry, &bd);
return 0;
}
+#ifdef CONFIG_PHYLIB
+
+static int ethoc_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+ struct ethoc *priv = bus->priv;
+ int rc;
+
+ ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(addr, reg));
+ ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
+
+ rc = wait_for_bit_le32(ethoc_reg(priv, MIISTATUS),
+ MIISTATUS_BUSY, false, CONFIG_SYS_HZ, false);
+
+ if (rc == 0) {
+ u32 data = ethoc_read(priv, MIIRX_DATA);
+
+ /* reset MII command register */
+ ethoc_write(priv, MIICOMMAND, 0);
+ return data;
+ }
+ return rc;
+}
+
+static int ethoc_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
+ u16 val)
+{
+ struct ethoc *priv = bus->priv;
+ int rc;
+
+ ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(addr, reg));
+ ethoc_write(priv, MIITX_DATA, val);
+ ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
+
+ rc = wait_for_bit_le32(ethoc_reg(priv, MIISTATUS),
+ MIISTATUS_BUSY, false, CONFIG_SYS_HZ, false);
+
+ if (rc == 0) {
+ /* reset MII command register */
+ ethoc_write(priv, MIICOMMAND, 0);
+ }
+ return rc;
+}
+
+static int ethoc_mdio_init(const char *name, struct ethoc *priv)
+{
+ struct mii_dev *bus = mdio_alloc();
+ int ret;
+
+ if (!bus) {
+ printf("Failed to allocate MDIO bus\n");
+ return -ENOMEM;
+ }
+
+ bus->read = ethoc_mdio_read;
+ bus->write = ethoc_mdio_write;
+ snprintf(bus->name, sizeof(bus->name), "%s", name);
+ bus->priv = priv;
+
+ ret = mdio_register(bus);
+ if (ret < 0)
+ return ret;
+
+ priv->bus = miiphy_get_dev_by_name(name);
+ return 0;
+}
+
+static int ethoc_phy_init(struct ethoc *priv, void *dev)
+{
+ struct phy_device *phydev;
+ int mask = 0xffffffff;
+
+#ifdef CONFIG_PHY_ADDR
+ mask = 1 << CONFIG_PHY_ADDR;
+#endif
+
+ phydev = phy_find_by_mask(priv->bus, mask, PHY_INTERFACE_MODE_MII);
+ if (!phydev)
+ return -ENODEV;
+
+ phy_connect_dev(phydev, dev);
+
+ phydev->supported &= PHY_BASIC_FEATURES;
+ phydev->advertising = phydev->supported;
+
+ priv->phydev = phydev;
+ phy_config(phydev);
+
+ return 0;
+}
+
+#else
+
+static inline int ethoc_mdio_init(const char *name, struct ethoc *priv)
+{
+ return 0;
+}
+
+static inline int ethoc_phy_init(struct ethoc *priv, void *dev)
+{
+ return 0;
+}
+
+#endif
+
#ifdef CONFIG_DM_ETH
static int ethoc_write_hwaddr(struct udevice *dev)
static void ethoc_stop(struct udevice *dev)
{
- struct ethoc *priv = dev_get_priv(dev);
-
- ethoc_disable_rx_and_tx(priv);
+ ethoc_stop_common(dev_get_priv(dev));
}
static int ethoc_ofdata_to_platdata(struct udevice *dev)
{
struct ethoc_eth_pdata *pdata = dev_get_platdata(dev);
+ fdt_addr_t addr;
- pdata->eth_pdata.iobase = dev_get_addr(dev);
+ pdata->eth_pdata.iobase = devfdt_get_addr(dev);
+ addr = devfdt_get_addr_index(dev, 1);
+ if (addr != FDT_ADDR_T_NONE)
+ pdata->packet_base = addr;
return 0;
}
struct ethoc *priv = dev_get_priv(dev);
priv->iobase = ioremap(pdata->eth_pdata.iobase, ETHOC_IOSIZE);
+ if (pdata->packet_base) {
+ priv->packet_phys = pdata->packet_base;
+ priv->packet = ioremap(pdata->packet_base,
+ (1 + PKTBUFSRX) * PKTSIZE_ALIGN);
+ }
+
+ ethoc_mdio_init(dev->name, priv);
+ ethoc_phy_init(priv, dev);
+
return 0;
}
{
struct ethoc *priv = dev_get_priv(dev);
+#ifdef CONFIG_PHYLIB
+ free(priv->phydev);
+ mdio_unregister(priv->bus);
+ mdio_free(priv->bus);
+#endif
iounmap(priv->iobase);
return 0;
}
priv->iobase = ioremap(dev->iobase, ETHOC_IOSIZE);
eth_register(dev);
+
+ ethoc_mdio_init(dev->name, priv);
+ ethoc_phy_init(priv, dev);
+
return 1;
}
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