PPC: Record U-Boot's relocated address in RAM and show in bdinfo.

[u-boot] / drivers / net / fec_mxc.c

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 446076fea117a39b71fa8ceded99e7f7dd441065..5af9cdba2ae5263421954c7ddae533722adfa4b2 100644 (file)
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -162,7 +162,9 @@ static int miiphy_restart_aneg(struct eth_device *dev)
         * Wake up from sleep if necessary
         * Reset PHY, then delay 300ns
         */
+#ifdef CONFIG_MX27
        miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_MIPGSR, 0x00FF);
+#endif
        miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR,
                        PHY_BMCR_RESET);
        udelay(1000);
@@ -363,7 +365,36 @@ static int fec_open(struct eth_device *edev)
        /*
         * Enable FEC-Lite controller
         */
-       writel(FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl);
+       writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
+               &fec->eth->ecntrl);
+#ifdef CONFIG_MX25
+       udelay(100);
+       /*
+        * setup the MII gasket for RMII mode
+        */
+
+       /* disable the gasket */
+       writew(0, &fec->eth->miigsk_enr);
+
+       /* wait for the gasket to be disabled */
+       while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
+               udelay(2);
+
+       /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
+       writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
+
+       /* re-enable the gasket */
+       writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
+
+       /* wait until MII gasket is ready */
+       int max_loops = 10;
+       while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
+               if (--max_loops <= 0) {
+                       printf("WAIT for MII Gasket ready timed out\n");
+                       break;
+               }
+       }
+#endif
 
        miiphy_wait_aneg(edev);
        miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR);
@@ -490,7 +521,7 @@ static void fec_halt(struct eth_device *dev)
        /*
         * issue graceful stop command to the FEC transmitter if necessary
         */
-       writel(FEC_ECNTRL_RESET | readl(&fec->eth->x_cntrl),
+       writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
                        &fec->eth->x_cntrl);
 
        debug("eth_halt: wait for stop regs\n");
@@ -498,7 +529,7 @@ static void fec_halt(struct eth_device *dev)
         * wait for graceful stop to register
         */
        while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
-               ;       /* FIXME ensure time */
+               udelay(1);
 
        /*
         * Disable SmartDMA tasks
@@ -510,7 +541,8 @@ static void fec_halt(struct eth_device *dev)
         * Disable the Ethernet Controller
         * Note: this will also reset the BD index counter!
         */
-       writel(0, &fec->eth->ecntrl);
+       writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
+                       &fec->eth->ecntrl);
        fec->rbd_index = 0;
        fec->tbd_index = 0;
        debug("eth_halt: done\n");
@@ -569,7 +601,7 @@ static int fec_send(struct eth_device *dev, volatile void* packet, int length)
         * wait until frame is sent .
         */
        while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
-               /* FIXME: Timeout */
+               udelay(1);
        }
        debug("fec_send: status 0x%x index %d\n",
                        readw(&fec->tbd_base[fec->tbd_index].status),
@@ -688,7 +720,7 @@ static int fec_probe(bd_t *bd)
        fec->xcv_type = MII100;
 
        /* Reset chip. */
-       writel(FEC_ECNTRL_RESET, &fec->eth->ecntrl);
+       writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
        while (readl(&fec->eth->ecntrl) & 1)
                udelay(10);