driver/nand:Define MAX_BANKS same as SoC defined for IFC

[u-boot] / drivers / net / fm / memac_phy.c

diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c
index ea6118b9b9953ed9fede92f71ef500d1750bf687..de9c0e9cd285558b1e21a4bc030b1b8d366d25e3 100644 (file)
--- a/drivers/net/fm/memac_phy.c
+++ b/drivers/net/fm/memac_phy.c
@@ -3,20 +3,7 @@
  *     Andy Fleming <afleming@freescale.com>
  *     Roy Zang <tie-fei.zang@freescale.com>
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  * Some part is taken from tsec.c
  */
 #include <common.h>
@@ -42,10 +29,8 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
                c45 = 0; /* clause 22 */
                dev_addr = regnum & 0x1f;
                clrbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
-       } else {
+       } else
                setbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
-               setbits_be32(&regs->mdio_stat, MDIO_STAT_HOLD_15_CLK);
-       }
 
        /* Wait till the bus is free */
        while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
@@ -89,10 +74,8 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
                c45 = 0; /* clause 22 */
                dev_addr = regnum & 0x1f;
                clrbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
-       } else {
+       } else
                setbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
-               setbits_be32(&regs->mdio_stat, MDIO_STAT_HOLD_15_CLK);
-       }
 
        /* Wait till the bus is free */
        while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
@@ -146,5 +129,17 @@ int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info)
 
        bus->priv = info->regs;
 
+       /*
+        * On some platforms like B4860, default value of MDIO_CLK_DIV bits
+        * in mdio_stat(mdio_cfg) register generates MDIO clock too high
+        * (much higher than 2.5MHz), violating the IEEE specs.
+        * On other platforms like T1040, default value of MDIO_CLK_DIV bits
+        * is zero, so MDIO clock is disabled.
+        * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
+        * be properly initialized.
+        */
+       setbits_be32(&((struct memac_mdio_controller *)info->regs)->mdio_stat,
+                    MDIO_STAT_CLKDIV(258));
+
        return mdio_register(bus);
 }