]> git.sur5r.net Git - u-boot/blobdiff - drivers/net/fm/t4240.c
net/fman: Add support for 10GEC3 and 10GEC4
[u-boot] / drivers / net / fm / t4240.c
index 10c141fa2634b0d266c6278d63966b1fc629ac29..1eacb22841e855f527d886213a7de134dad8d7e2 100644 (file)
@@ -49,6 +49,13 @@ void fman_disable_port(enum fm_port port)
        setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
 }
 
+void fman_enable_port(enum fm_port port)
+{
+       ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+       clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
+}
+
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
        ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -114,7 +121,45 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
                        return PHY_INTERFACE_MODE_SGMII;
                break;
        default:
-               return PHY_INTERFACE_MODE_NONE;
+               break;
+       }
+
+       /* handle QSGMII */
+       switch (port) {
+       case FM1_DTSEC1:
+       case FM1_DTSEC2:
+       case FM1_DTSEC3:
+       case FM1_DTSEC4:
+               /* check lane G on SerDes1 */
+               if (is_serdes_configured(QSGMII_FM1_A))
+                       return PHY_INTERFACE_MODE_QSGMII;
+               break;
+       case FM1_DTSEC5:
+       case FM1_DTSEC6:
+       case FM1_DTSEC9:
+       case FM1_DTSEC10:
+               /* check lane C on SerDes1 */
+               if (is_serdes_configured(QSGMII_FM1_B))
+                       return PHY_INTERFACE_MODE_QSGMII;
+               break;
+       case FM2_DTSEC1:
+       case FM2_DTSEC2:
+       case FM2_DTSEC3:
+       case FM2_DTSEC4:
+               /* check lane G on SerDes2 */
+               if (is_serdes_configured(QSGMII_FM2_A))
+                       return PHY_INTERFACE_MODE_QSGMII;
+               break;
+       case FM2_DTSEC5:
+       case FM2_DTSEC6:
+       case FM2_DTSEC9:
+       case FM2_DTSEC10:
+               /* check lane C on SerDes2 */
+               if (is_serdes_configured(QSGMII_FM2_B))
+                       return PHY_INTERFACE_MODE_QSGMII;
+               break;
+       default:
+               break;
        }
 
        return PHY_INTERFACE_MODE_NONE;