* until the write is done before it returns. All PHY configuration has to be
* done through the TSEC1 MIIM regs
*/
-int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
- int regnum, u16 value)
+static int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
+ int regnum, u16 value)
{
u32 mdio_ctl;
u32 stat_val;
* Clears miimcom first. All PHY configuration has to be done through the
* TSEC1 MIIM regs
*/
-int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
- int regnum)
+static int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
+ int regnum)
{
u32 mdio_ctl;
u32 stat_val;
return in_be32(®s->mdio_data) & 0xffff;
}
-int tgec_mdio_reset(struct mii_dev *bus)
+static int tgec_mdio_reset(struct mii_dev *bus)
{
return 0;
}