}
#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+
+__weak bool soc_has_aiop(void)
+{
+ return false;
+}
+
static int load_mc_aiop_img(u64 aiop_fw_addr)
{
u64 mc_ram_addr = mc_get_dram_addr();
void *aiop_img;
#endif
+ /* Check if AIOP is available */
+ if (!soc_has_aiop())
+ return -ENODEV;
/*
* Load the MC AIOP image in the MC private DRAM block:
*/
/*
* Management Complex cores should be held at reset out of POR.
- * U-boot should be the first software to touch MC. To be safe,
+ * U-Boot should be the first software to touch MC. To be safe,
* we reset all cores again by setting GCR1 to 0. It doesn't do
* anything if they are held at reset. After we setup the firmware
* we kick off MC by deasserting the reset bit for core 0, and
err_get_swp_init:
dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
err_get_enable:
- free(dflt_dpio);
err_get_attr:
dpio_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
dpio_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
err_create:
+ free(dflt_dpio);
err_malloc:
return err;
}
{
int err = 0;
- if (bd && get_mc_boot_status() == -1)
+ /* MC is not loaded intentionally, So return success. */
+ if (bd && get_mc_boot_status() != 0)
return 0;
if (bd && !get_mc_boot_status() && get_dpl_apply_status() == -1) {
aiop_fw_addr = simple_strtoull(argv[3], NULL,
16);
+ /* if SoC doesn't have AIOP, err = -ENODEV */
err = load_mc_aiop_img(aiop_fw_addr);
if (!err)
printf("fsl-mc: AIOP FW applied\n");