clk: Add Actions Semi OWL clock support

[u-boot] / drivers / net / gmac_rockchip.c

diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 551c2309ad4f904858f7a472996da6f88a0c9371..30a24d1947e6bb76d07eaccc50f96582c05f9372 100644 (file)
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
  *
- * SPDX-License-Identifier:    GPL-2.0+
- *
  * Rockchip GMAC ethernet IP driver for U-Boot
  */
 
@@ -15,6 +14,7 @@
 #include <asm/arch/periph.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/grf_rk322x.h>
 #include <asm/arch/grf_rk3288.h>
 #include <asm/arch/grf_rk3328.h>
 #include <asm/arch/grf_rk3368.h>
@@ -24,8 +24,6 @@
 #include <dt-bindings/clock/rk3288-cru.h>
 #include "designware.h"
 
-DECLARE_GLOBAL_DATA_PTR;
-
 /*
  * Platform data for the gmac
  *
@@ -69,6 +67,39 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
        return designware_eth_ofdata_to_platdata(dev);
 }
 
+static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+{
+       struct rk322x_grf *grf;
+       int clk;
+       enum {
+               RK3228_GMAC_CLK_SEL_SHIFT = 8,
+               RK3228_GMAC_CLK_SEL_MASK  = GENMASK(9, 8),
+               RK3228_GMAC_CLK_SEL_125M  = 0 << 8,
+               RK3228_GMAC_CLK_SEL_25M   = 3 << 8,
+               RK3228_GMAC_CLK_SEL_2_5M  = 2 << 8,
+       };
+
+       switch (priv->phydev->speed) {
+       case 10:
+               clk = RK3228_GMAC_CLK_SEL_2_5M;
+               break;
+       case 100:
+               clk = RK3228_GMAC_CLK_SEL_25M;
+               break;
+       case 1000:
+               clk = RK3228_GMAC_CLK_SEL_125M;
+               break;
+       default:
+               debug("Unknown phy speed: %d\n", priv->phydev->speed);
+               return -EINVAL;
+       }
+
+       grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+       rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk);
+
+       return 0;
+}
+
 static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 {
        struct rk3288_grf *grf;
@@ -221,6 +252,50 @@ static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
        return 0;
 }
 
+static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+       struct rk322x_grf *grf;
+       enum {
+               RK3228_RMII_MODE_SHIFT = 10,
+               RK3228_RMII_MODE_MASK  = BIT(10),
+
+               RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4,
+               RK3228_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
+               RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
+
+               RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
+               RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+               RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
+
+               RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
+               RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+               RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
+       };
+       enum {
+               RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
+               RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
+
+               RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
+               RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
+       };
+
+       grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+       rk_clrsetreg(&grf->mac_con[1],
+                    RK3228_RMII_MODE_MASK |
+                    RK3228_GMAC_PHY_INTF_SEL_MASK |
+                    RK3228_RXCLK_DLY_ENA_GMAC_MASK |
+                    RK3228_TXCLK_DLY_ENA_GMAC_MASK,
+                    RK3228_GMAC_PHY_INTF_SEL_RGMII |
+                    RK3228_RXCLK_DLY_ENA_GMAC_ENABLE |
+                    RK3228_TXCLK_DLY_ENA_GMAC_ENABLE);
+
+       rk_clrsetreg(&grf->mac_con[0],
+                    RK3228_CLK_RX_DL_CFG_GMAC_MASK |
+                    RK3228_CLK_TX_DL_CFG_GMAC_MASK,
+                    pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT |
+                    pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 {
        struct rk3288_grf *grf;
@@ -448,6 +523,11 @@ const struct eth_ops gmac_rockchip_eth_ops = {
        .write_hwaddr           = designware_eth_write_hwaddr,
 };
 
+const struct rk_gmac_ops rk3228_gmac_ops = {
+       .fix_mac_speed = rk3228_gmac_fix_mac_speed,
+       .set_to_rgmii = rk3228_gmac_set_to_rgmii,
+};
+
 const struct rk_gmac_ops rk3288_gmac_ops = {
        .fix_mac_speed = rk3288_gmac_fix_mac_speed,
        .set_to_rgmii = rk3288_gmac_set_to_rgmii,
@@ -474,6 +554,8 @@ const struct rk_gmac_ops rv1108_gmac_ops = {
 };
 
 static const struct udevice_id rockchip_gmac_ids[] = {
+       { .compatible = "rockchip,rk3228-gmac",
+         .data = (ulong)&rk3228_gmac_ops },
        { .compatible = "rockchip,rk3288-gmac",
          .data = (ulong)&rk3288_gmac_ops },
        { .compatible = "rockchip,rk3328-gmac",