return -EFAULT;
}
+ /* write the phy and reg addressse into the MII address reg */
+ writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
+ ®s->madr);
+
+ /* write data to the MII write register */
+ writel(data, ®s->mwtd);
+
/* wait till the MII is not busy */
timeout = MII_TIMEOUT;
do {
return -EFAULT;
}
- /* write the phy and reg addressse into the MII address reg */
- writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
- ®s->madr);
-
- /* write data to the MII write register */
- writel(data, ®s->mwtd);
-
/*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr,
reg_ofs, data);*/
#endif
/*
+ * Provide default Ethernet buffers base address if target did not.
* Locate buffers in SRAM at 0x00001000 to avoid cache issues and
* maximize throughput.
*/
-
-#define LPC32XX_ETH_BUFS 0x00001000
+#if !defined(CONFIG_LPC32XX_ETH_BUFS_BASE)
+#define CONFIG_LPC32XX_ETH_BUFS_BASE 0x00001000
+#endif
static struct lpc32xx_eth_device lpc32xx_eth = {
.regs = (struct lpc32xx_eth_registers *)LPC32XX_ETH_BASE,
- .bufs = (struct lpc32xx_eth_buffers *)LPC32XX_ETH_BUFS,
+ .bufs = (struct lpc32xx_eth_buffers *)CONFIG_LPC32XX_ETH_BUFS_BASE,
#if defined(CONFIG_RMII)
.phy_rmii = true,
#endif
}
bus->read = lpc32xx_eth_phy_read;
bus->write = lpc32xx_eth_phy_write;
- sprintf(bus->name, dev->name);
+ strcpy(bus->name, dev->name);
ret = mdio_register(bus);
if (ret) {