#define DEBUG 0
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
- defined(CONFIG_MPC512x_FEC)
-
#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
#error "CONFIG_MII has to be defined!"
#endif
-int fec512x_miiphy_read(char *devname, u8 phyAddr, u8 regAddr, u16 * retVal);
-int fec512x_miiphy_write(char *devname, u8 phyAddr, u8 regAddr, u16 data);
+int fec512x_miiphy_read(struct mii_dev *bus, int phyAddr, int devad,
+ int regAddr);
+int fec512x_miiphy_write(struct mii_dev *bus, int phyAddr, int devad,
+ int regAddr, u16 data);
int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis);
static uchar rx_buff[FEC_BUFFER_SIZE];
* and do not drop the Preamble.
*/
out_be32(&fec->eth->mii_speed,
- (((gd->ips_clk / 1000000) / 5) + 1) << 1);
+ (((gd->arch.ips_clk / 1000000) / 5) + 1) << 1);
/*
* Reset PHY, then delay 300ns
/********************************************************************/
-static int mpc512x_fec_send (struct eth_device *dev, volatile void *eth_data,
- int data_length)
+static int mpc512x_fec_send(struct eth_device *dev, void *eth_data,
+ int data_length)
{
/*
* This routine transmits one frame. This routine only accepts
/* Graceful stop complete */
if (in_be32(&fec->eth->x_cntrl) & 0x00000001) {
mpc512x_fec_halt (dev);
- clrbits_be32(&fec->eth->x_cntrl, 0x00000001);;
+ clrbits_be32(&fec->eth->x_cntrl, 0x00000001);
mpc512x_fec_init (dev, NULL);
}
}
rx_buff_idx = frame_length;
if (pRbd->status & FEC_RBD_LAST) {
- NetReceive ((uchar*)rx_buff, frame_length);
+ net_process_received_packet((uchar *)rx_buff,
+ frame_length);
rx_buff_idx = 0;
}
}
dev->send = mpc512x_fec_send;
dev->recv = mpc512x_fec_recv;
- sprintf (dev->name, "FEC ETHERNET");
+ strcpy(dev->name, "FEC");
eth_register (dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
- miiphy_register (dev->name,
- fec512x_miiphy_read, fec512x_miiphy_write);
+ int retval;
+ struct mii_dev *mdiodev = mdio_alloc();
+ if (!mdiodev)
+ return -ENOMEM;
+ strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+ mdiodev->read = fec512x_miiphy_read;
+ mdiodev->write = fec512x_miiphy_write;
+
+ retval = mdio_register(mdiodev);
+ if (retval < 0)
+ return retval;
#endif
/* Clean up space FEC's MIB and FIFO RAM ...*/
/* MII-interface related functions */
/********************************************************************/
-int fec512x_miiphy_read (char *devname, u8 phyAddr, u8 regAddr, u16 * retVal)
+int fec512x_miiphy_read(struct mii_dev *bus, int phyAddr, int devad,
+ int regAddr)
{
+ u16 retVal = 0;
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile fec512x_t *eth = &im->fec;
u32 reg; /* convenient holder for the PHY register */
/*
* it's now safe to read the PHY's register
*/
- *retVal = (u16) in_be32(ð->mii_data);
+ retVal = (u16) in_be32(ð->mii_data);
- return 0;
+ return retVal;
}
/********************************************************************/
-int fec512x_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data)
+int fec512x_miiphy_write(struct mii_dev *bus, int phyAddr, int devad,
+ int regAddr, u16 data)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile fec512x_t *eth = &im->fec;
return 0;
}
-
-#endif /* CONFIG_MPC512x_FEC */