arm: mach-omap2: Generate MLO file from SD boot capable targets

[u-boot] / drivers / net / mpc512x_fec.c

diff --git a/drivers/net/mpc512x_fec.c b/drivers/net/mpc512x_fec.c
index e850672a4ffbd16af02924ae3e90abb2d23d0285..a18b959425620b5aa0da255c8e2ff191dc059a9a 100644 (file)
--- a/drivers/net/mpc512x_fec.c
+++ b/drivers/net/mpc512x_fec.c
@@ -22,8 +22,10 @@ DECLARE_GLOBAL_DATA_PTR;
 #error "CONFIG_MII has to be defined!"
 #endif
 
-int fec512x_miiphy_read(const char *devname, u8 phyAddr, u8 regAddr, u16 * retVal);
-int fec512x_miiphy_write(const char *devname, u8 phyAddr, u8 regAddr, u16 data);
+int fec512x_miiphy_read(struct mii_dev *bus, int phyAddr, int devad,
+                       int regAddr);
+int fec512x_miiphy_write(struct mii_dev *bus, int phyAddr, int devad,
+                        int regAddr, u16 data);
 int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis);
 
 static uchar rx_buff[FEC_BUFFER_SIZE];
@@ -557,7 +559,7 @@ static int mpc512x_fec_recv (struct eth_device *dev)
                /* Graceful stop complete */
                if (in_be32(&fec->eth->x_cntrl) & 0x00000001) {
                        mpc512x_fec_halt (dev);
-                       clrbits_be32(&fec->eth->x_cntrl, 0x00000001);;
+                       clrbits_be32(&fec->eth->x_cntrl, 0x00000001);
                        mpc512x_fec_init (dev, NULL);
                }
        }
@@ -639,8 +641,17 @@ int mpc512x_fec_initialize (bd_t * bis)
        eth_register (dev);
 
 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-       miiphy_register (dev->name,
-                       fec512x_miiphy_read, fec512x_miiphy_write);
+       int retval;
+       struct mii_dev *mdiodev = mdio_alloc();
+       if (!mdiodev)
+               return -ENOMEM;
+       strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
+       mdiodev->read = fec512x_miiphy_read;
+       mdiodev->write = fec512x_miiphy_write;
+
+       retval = mdio_register(mdiodev);
+       if (retval < 0)
+               return retval;
 #endif
 
        /* Clean up space FEC's MIB and FIFO RAM ...*/
@@ -670,8 +681,10 @@ int mpc512x_fec_initialize (bd_t * bis)
 
 /* MII-interface related functions */
 /********************************************************************/
-int fec512x_miiphy_read(const char *devname, u8 phyAddr, u8 regAddr, u16 *retVal)
+int fec512x_miiphy_read(struct mii_dev *bus, int phyAddr, int devad,
+                       int regAddr)
 {
+       u16 retVal = 0;
        volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
        volatile fec512x_t *eth = &im->fec;
        u32 reg;                /* convenient holder for the PHY register */
@@ -711,13 +724,14 @@ int fec512x_miiphy_read(const char *devname, u8 phyAddr, u8 regAddr, u16 *retVal
        /*
         * it's now safe to read the PHY's register
         */
-       *retVal = (u16) in_be32(&eth->mii_data);
+       retVal = (u16) in_be32(&eth->mii_data);
 
-       return 0;
+       return retVal;
 }
 
 /********************************************************************/
-int fec512x_miiphy_write(const char *devname, u8 phyAddr, u8 regAddr, u16 data)
+int fec512x_miiphy_write(struct mii_dev *bus, int phyAddr, int devad,
+                        int regAddr, u16 data)
 {
        volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
        volatile fec512x_t *eth = &im->fec;