/*
- * (C) Copyright 2003-2007
+ * (C) Copyright 2003-2009
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Derived from the MPC8xx FEC driver.
*/
#include <common.h>
-#include <mpc512x.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
#endif
#if (DEBUG & 0x40)
-static uint32 local_crc32(char *string, unsigned int crc_value, int len);
+static u32 local_crc32(char *string, unsigned int crc_value, int len);
#endif
-int fec512x_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal);
-int fec512x_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
+int fec512x_miiphy_read(char *devname, u8 phyAddr, u8 regAddr, u16 * retVal);
+int fec512x_miiphy_write(char *devname, u8 phyAddr, u8 regAddr, u16 data);
int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis);
static uchar rx_buff[FEC_BUFFER_SIZE];
#if (DEBUG & 0x2)
static void mpc512x_fec_phydump (char *devname)
{
- uint16 phyStatus, i;
- uint8 phyAddr = CONFIG_PHY_ADDR;
- uint8 reg_mask[] = {
+ u16 phyStatus, i;
+ u8 phyAddr = CONFIG_PHY_ADDR;
+ u8 reg_mask[] = {
/* regs to print: 0...8, 21,27,31 */
1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1,
*/
for (ix = 0; ix < FEC_RBD_NUM; ix++) {
fec->bdBase->rbd[ix].dataPointer =
- (uint32)&fec->bdBase->recv_frames[ix];
+ (u32)&fec->bdBase->recv_frames[ix];
fec->bdBase->rbd[ix].status = FEC_RBD_EMPTY;
fec->bdBase->rbd[ix].dataLength = 0;
}
/********************************************************************/
static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, char *mac)
{
- uint8 currByte; /* byte for which to compute the CRC */
+ u8 currByte; /* byte for which to compute the CRC */
int byte; /* loop - counter */
int bit; /* loop - counter */
- uint32 crc = 0xffffffff; /* initial value */
+ u32 crc = 0xffffffff; /* initial value */
/*
* The algorithm used is the following:
out_be32(&fec->eth->r_buff_size, FEC_BUFFER_SIZE);
/* Setup BD base addresses */
- out_be32(&fec->eth->r_des_start, (uint32)fec->bdBase->rbd);
- out_be32(&fec->eth->x_des_start, (uint32)fec->bdBase->tbd);
+ out_be32(&fec->eth->r_des_start, (u32)fec->bdBase->rbd);
+ out_be32(&fec->eth->x_des_start, (u32)fec->bdBase->tbd);
/* DMA Control */
out_be32(&fec->eth->dma_control, 0xc0000000);
int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis)
{
mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
- const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
+ const u8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
int timeout = 1;
- uint16 phyStatus;
+ u16 phyStatus;
#if (DEBUG & 0x1)
printf ("mpc512x_fec_init_phy... Begin\n");
*/
pTbd = &fec->bdBase->tbd[fec->tbdIndex];
pTbd->dataLength = data_length;
- pTbd->dataPointer = (uint32)eth_data;
+ pTbd->dataPointer = (u32)eth_data;
pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
printf ("recv data length 0x%08x data hdr: ",
pRbd->dataLength);
for (i = 0; i < 14; i++)
- printf ("%x ", *((uint8*)pRbd->dataPointer + i));
+ printf ("%x ", *((u8*)pRbd->dataPointer + i));
printf("\n");
}
#endif
/********************************************************************/
int mpc512x_fec_initialize (bd_t * bis)
{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
mpc512x_fec_priv *fec;
struct eth_device *dev;
int i;
dev = (struct eth_device *) malloc (sizeof(*dev));
memset (dev, 0, sizeof *dev);
- fec->eth = (ethernet_regs *) MPC512X_FEC;
+ fec->eth = &im->fec;
# ifndef CONFIG_FEC_10MBIT
fec->xcv_type = MII100;
fec->xcv_type = MII10;
# endif
dev->priv = (void *)fec;
- dev->iobase = MPC512X_FEC;
+ dev->iobase = (int)&im->fec;
dev->init = mpc512x_fec_init;
dev->halt = mpc512x_fec_halt;
dev->send = mpc512x_fec_send;
#endif
/* Clean up space FEC's MIB and FIFO RAM ...*/
- memset ((void *) MPC512X_FEC + 0x200, 0x00, 0x400);
+ memset ((void *)&im->fec.mib, 0x00, sizeof(im->fec.mib));
+ memset ((void *)&im->fec.fifo, 0x00, sizeof(im->fec.fifo));
/*
* Malloc space for BDs (must be quad word-aligned)
* this pointer is lost, so cannot be freed
*/
bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f);
- fec->bdBase = (mpc512x_buff_descs*)((uint32)bd & 0xfffffff0);
+ fec->bdBase = (mpc512x_buff_descs*)((u32)bd & 0xfffffff0);
memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f);
/*
/* MII-interface related functions */
/********************************************************************/
-int fec512x_miiphy_read (char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
+int fec512x_miiphy_read (char *devname, u8 phyAddr, u8 regAddr, u16 * retVal)
{
- ethernet_regs *eth = (ethernet_regs *) MPC512X_FEC;
- uint32 reg; /* convenient holder for the PHY register */
- uint32 phy; /* convenient holder for the PHY */
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ volatile fec512x_t *eth = &im->fec;
+ u32 reg; /* convenient holder for the PHY register */
+ u32 phy; /* convenient holder for the PHY */
int timeout = 0xffff;
/*
/*
* it's now safe to read the PHY's register
*/
- *retVal = (uint16) in_be32(ð->mii_data);
+ *retVal = (u16) in_be32(ð->mii_data);
return 0;
}
/********************************************************************/
-int fec512x_miiphy_write (char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
+int fec512x_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data)
{
- ethernet_regs *eth = (ethernet_regs *) MPC512X_FEC;
- uint32 reg; /* convenient holder for the PHY register */
- uint32 phy; /* convenient holder for the PHY */
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ volatile fec512x_t *eth = &im->fec;
+ u32 reg; /* convenient holder for the PHY register */
+ u32 phy; /* convenient holder for the PHY */
int timeout = 0xffff;
reg = regAddr << FEC_MII_DATA_RA_SHIFT;
}
#if (DEBUG & 0x40)
-static uint32 local_crc32 (char *string, unsigned int crc_value, int len)
+static u32 local_crc32 (char *string, unsigned int crc_value, int len)
{
int i;
char c;
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