/* Ports using BM pool */
u32 port_map;
-
- /* Occupied buffers indicator */
- int in_use_thresh;
};
/* Static declaractions */
/* Update BM driver with number of buffers added to pool */
bm_pool->buf_num += i;
- bm_pool->in_use_thresh = bm_pool->buf_num / 4;
return i;
}
val |= MVPP2_GMAC_INBAND_AN_MASK;
break;
case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
val |= MVPP2_GMAC_PORT_RGMII_MASK;
default:
val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
if (priv->hw_version == MVPP22)
mvpp2_axi_init(priv);
- /* Disable HW PHY polling */
if (priv->hw_version == MVPP21) {
+ /* Disable HW PHY polling */
val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
} else {
+ /* Enable HW PHY polling */
val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
- val &= ~MVPP22_SMI_POLLING_EN;
+ val |= MVPP22_SMI_POLLING_EN;
writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
}
mvpp2_cleanup_txqs(port);
}
+static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port)
+{
+ writel(port->phyaddr, port->priv->iface_base +
+ MVPP22_SMI_PHY_ADDR_REG(port->gop_id));
+
+ return 0;
+}
+
static int mvpp2_base_probe(struct udevice *dev)
{
struct mvpp2 *priv = dev_get_priv(dev);
port->base = priv->iface_base + MVPP22_PORT_BASE +
port->gop_id * MVPP22_PORT_OFFSET;
+ /* Set phy address of the port */
+ mvpp22_smi_phy_addr_cfg(port);
+
/* GoP Init */
gop_port_init(port);
}