mvpp2: Fix warning over 32bit vs 64bit targets

[u-boot] / drivers / net / mvpp2.c

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 426b2c2dce29b58b07921c163eaf789c77b42368..e3d31a560d54af4697cf8d48d678e878b4dd3fae 100644 (file)
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -316,6 +316,8 @@ do {                                                                        \
 #define            MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK   0xff00
 #define     MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
 #define MVPP22_BM_MC_RLS_REG                   0x64d4
+#define MVPP22_BM_POOL_BASE_HIGH_REG           0x6310
+#define MVPP22_BM_POOL_BASE_HIGH_MASK          0xff
 
 /* TX Scheduler registers */
 #define MVPP2_TXP_SCHED_PORT_INDEX_REG         0x8000
@@ -617,10 +619,10 @@ enum mv_netc_lanes {
 #define MVPP2_MAX_TXD                  16
 
 /* Amount of Tx descriptors that can be reserved at once by CPU */
-#define MVPP2_CPU_DESC_CHUNK           64
+#define MVPP2_CPU_DESC_CHUNK           16
 
 /* Max number of Tx descriptors in each aggregated queue */
-#define MVPP2_AGGR_TXQ_SIZE            256
+#define MVPP2_AGGR_TXQ_SIZE            16
 
 /* Descriptor aligned size */
 #define MVPP2_DESC_ALIGNED_SIZE                32
@@ -2594,6 +2596,10 @@ static int mvpp2_bm_pool_create(struct udevice *dev,
 
        mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
                    lower_32_bits(bm_pool->dma_addr));
+       if (priv->hw_version == MVPP22)
+               mvpp2_write(priv, MVPP22_BM_POOL_BASE_HIGH_REG,
+                           (upper_32_bits(bm_pool->dma_addr) &
+                           MVPP22_BM_POOL_BASE_HIGH_MASK));
        mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
 
        val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
@@ -2669,7 +2675,7 @@ static int mvpp2_bm_pools_init(struct udevice *dev,
                err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
                if (err)
                        goto err_unroll_pools;
-               mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
+               mvpp2_bm_pool_bufsize_set(priv, bm_pool, RX_BUFFER_SIZE);
        }
        return 0;
 
@@ -2855,9 +2861,6 @@ mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
                }
        }
 
-       mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
-                                 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
-
        return new_pool;
 }
 
@@ -4681,20 +4684,6 @@ static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
                port->rxqs[queue] = rxq;
        }
 
-       /* Configure Rx queue group interrupt for this port */
-       if (priv->hw_version == MVPP21) {
-               mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
-                           CONFIG_MV_ETH_RXQ);
-       } else {
-               u32 val;
-
-               val = (port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
-               mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
-
-               val = (CONFIG_MV_ETH_RXQ <<
-                      MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
-               mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
-       }
 
        /* Create Rx descriptor rings */
        for (queue = 0; queue < rxq_number; queue++) {
@@ -4733,7 +4722,7 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
        u32 id;
        u32 phyaddr = 0;
        int phy_mode = -1;
-       u64 mdio_addr;
+       phys_addr_t mdio_addr;
 
        phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
 
@@ -5014,13 +5003,14 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
                return -EINVAL;
        }
 
-       /* MBUS windows configuration */
-       dram_target_info = mvebu_mbus_dram_info();
-       if (dram_target_info)
-               mvpp2_conf_mbus_windows(dram_target_info, priv);
-
        if (priv->hw_version == MVPP22)
                mvpp2_axi_init(priv);
+       else {
+               /* MBUS windows configuration */
+               dram_target_info = mvebu_mbus_dram_info();
+               if (dram_target_info)
+                       mvpp2_conf_mbus_windows(dram_target_info, priv);
+       }
 
        if (priv->hw_version == MVPP21) {
                /* Disable HW PHY polling */
@@ -5057,25 +5047,6 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
        if (priv->hw_version == MVPP22)
                mvpp2_tx_fifo_init(priv);
 
-       /* Reset Rx queue group interrupt configuration */
-       for (i = 0; i < MVPP2_MAX_PORTS; i++) {
-               if (priv->hw_version == MVPP21) {
-                       mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(i),
-                                   CONFIG_MV_ETH_RXQ);
-                       continue;
-               } else {
-                       u32 val;
-
-                       val = (i << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
-                       mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
-
-                       val = (CONFIG_MV_ETH_RXQ <<
-                              MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
-                       mvpp2_write(priv,
-                                   MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
-               }
-       }
-
        if (priv->hw_version == MVPP21)
                writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
                       priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
@@ -5221,21 +5192,10 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
        int pool, rx_bytes, err;
        int rx_received;
        struct mvpp2_rx_queue *rxq;
-       u32 cause_rx_tx, cause_rx, cause_misc;
        u8 *data;
 
-       cause_rx_tx = mvpp2_read(port->priv,
-                                MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
-       cause_rx_tx &= ~MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
-       cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
-       if (!cause_rx_tx && !cause_misc)
-               return 0;
-
-       cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
-
        /* Process RX packets */
-       cause_rx |= port->pending_cause_rx;
-       rxq = mvpp2_get_rx_queue(port, cause_rx);
+       rxq = port->rxqs[0];
 
        /* Get number of received packets and clamp the to-do */
        rx_received = mvpp2_rxq_received(port, rxq->id);
@@ -5291,21 +5251,6 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
        return rx_bytes;
 }
 
-/* Drain Txq */
-static void mvpp2_txq_drain(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
-                           int enable)
-{
-       u32 val;
-
-       mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
-       val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
-       if (enable)
-               val |= MVPP2_TXQ_DRAIN_EN_MASK;
-       else
-               val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
-       mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
-}
-
 static int mvpp2_send(struct udevice *dev, void *packet, int length)
 {
        struct mvpp2_port *port = dev_get_priv(dev);
@@ -5349,9 +5294,6 @@ static int mvpp2_send(struct udevice *dev, void *packet, int length)
                tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
        } while (tx_done);
 
-       /* Enable TXQ drain */
-       mvpp2_txq_drain(port, txq, 1);
-
        timeout = 0;
        do {
                if (timeout++ > 10000) {
@@ -5361,9 +5303,6 @@ static int mvpp2_send(struct udevice *dev, void *packet, int length)
                tx_done = mvpp2_txq_sent_desc_proc(port, txq);
        } while (!tx_done);
 
-       /* Disable TXQ drain */
-       mvpp2_txq_drain(port, txq, 0);
-
        return 0;
 }