*/
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <miiphy.h>
#include <linux/mii.h>
#include <wait_bit.h>
#include <asm/io.h>
+#include <asm/gpio.h>
/* Registers */
#define RAVB_REG_CCC 0x000
struct phy_device *phydev;
struct mii_dev *bus;
void __iomem *iobase;
+ struct clk clk;
+ struct gpio_desc reset_gpio;
};
static inline void ravb_flush_dcache(u32 addr, u32 len)
writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);
/* Check the operating mode is changed to the config mode. */
- return wait_for_bit(dev->name, (void *)eth->iobase + RAVB_REG_CSR,
- CSR_OPS_CONFIG, true, 100, true);
+ return wait_for_bit_le32(eth->iobase + RAVB_REG_CSR,
+ CSR_OPS_CONFIG, true, 100, true);
}
static void ravb_base_desc_init(struct ravb_priv *eth)
struct ravb_priv *eth = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_platdata(dev);
struct phy_device *phydev;
- int reg;
+ int mask = 0xffffffff, reg;
- phydev = phy_connect(eth->bus, pdata->phy_interface,
- dev, PHY_INTERFACE_MODE_RGMII_ID);
+ if (dm_gpio_is_valid(ð->reset_gpio)) {
+ dm_gpio_set_value(ð->reset_gpio, 1);
+ mdelay(20);
+ dm_gpio_set_value(ð->reset_gpio, 0);
+ mdelay(1);
+ }
+
+ phydev = phy_find_by_mask(eth->bus, mask, pdata->phy_interface);
if (!phydev)
return -ENODEV;
+ phy_connect_dev(phydev, dev);
+
eth->phydev = phydev;
/* 10BASE is not supported for Ethernet AVB MAC */
return 0;
}
-int ravb_start(struct udevice *dev)
+static int ravb_start(struct udevice *dev)
{
struct ravb_priv *eth = dev_get_priv(dev);
int ret;
- ret = ravb_reset(dev);
+ ret = clk_enable(ð->clk);
if (ret)
return ret;
+ ret = ravb_reset(dev);
+ if (ret)
+ goto err;
+
ravb_base_desc_init(eth);
ravb_tx_desc_init(eth);
ravb_rx_desc_init(eth);
ret = ravb_config(dev);
if (ret)
- return ret;
+ goto err;
/* Setting the control will start the AVB-DMAC process. */
writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC);
return 0;
+
+err:
+ clk_disable(ð->clk);
+ return ret;
}
static void ravb_stop(struct udevice *dev)
{
+ struct ravb_priv *eth = dev_get_priv(dev);
+
ravb_reset(dev);
+ clk_disable(ð->clk);
}
static int ravb_probe(struct udevice *dev)
iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
eth->iobase = iobase;
+ ret = clk_get_by_index(dev, 0, ð->clk);
+ if (ret < 0)
+ goto err_mdio_alloc;
+
+ gpio_request_by_name(dev, "reset-gpios", 0, ð->reset_gpio,
+ GPIOD_IS_OUT);
+
mdiodev = mdio_alloc();
if (!mdiodev) {
ret = -ENOMEM;
free(eth->phydev);
mdio_unregister(eth->bus);
mdio_free(eth->bus);
+ if (dm_gpio_is_valid(ð->reset_gpio))
+ dm_gpio_free(dev, ð->reset_gpio);
unmap_physmem(eth->iobase, MAP_NOCACHE);
return 0;
.write_hwaddr = ravb_write_hwaddr,
};
+int ravb_ofdata_to_platdata(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ const char *phy_mode;
+ const fdt32_t *cell;
+ int ret = 0;
+
+ pdata->iobase = devfdt_get_addr(dev);
+ pdata->phy_interface = -1;
+ phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
+ NULL);
+ if (phy_mode)
+ pdata->phy_interface = phy_get_interface_by_name(phy_mode);
+ if (pdata->phy_interface == -1) {
+ debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ return -EINVAL;
+ }
+
+ pdata->max_speed = 1000;
+ cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
+ if (cell)
+ pdata->max_speed = fdt32_to_cpu(*cell);
+
+ sprintf(bb_miiphy_buses[0].name, dev->name);
+
+ return ret;
+}
+
+static const struct udevice_id ravb_ids[] = {
+ { .compatible = "renesas,etheravb-r8a7795" },
+ { .compatible = "renesas,etheravb-r8a7796" },
+ { .compatible = "renesas,etheravb-r8a77970" },
+ { .compatible = "renesas,etheravb-r8a77995" },
+ { .compatible = "renesas,etheravb-rcar-gen3" },
+ { }
+};
+
U_BOOT_DRIVER(eth_ravb) = {
.name = "ravb",
.id = UCLASS_ETH,
+ .of_match = ravb_ids,
+ .ofdata_to_platdata = ravb_ofdata_to_platdata,
.probe = ravb_probe,
.remove = ravb_remove,
.ops = &ravb_ops,