#include <linux/mii.h>
#include <wait_bit.h>
#include <asm/io.h>
+#include <asm/gpio.h>
/* Registers */
#define RAVB_REG_CCC 0x000
struct mii_dev *bus;
void __iomem *iobase;
struct clk clk;
+ struct gpio_desc reset_gpio;
};
static inline void ravb_flush_dcache(u32 addr, u32 len)
writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);
/* Check the operating mode is changed to the config mode. */
- return wait_for_bit(dev->name, (void *)eth->iobase + RAVB_REG_CSR,
- CSR_OPS_CONFIG, true, 100, true);
+ return wait_for_bit_le32(eth->iobase + RAVB_REG_CSR,
+ CSR_OPS_CONFIG, true, 100, true);
}
static void ravb_base_desc_init(struct ravb_priv *eth)
struct phy_device *phydev;
int mask = 0xffffffff, reg;
+ if (dm_gpio_is_valid(ð->reset_gpio)) {
+ dm_gpio_set_value(ð->reset_gpio, 1);
+ mdelay(20);
+ dm_gpio_set_value(ð->reset_gpio, 0);
+ mdelay(1);
+ }
+
phydev = phy_find_by_mask(eth->bus, mask, pdata->phy_interface);
if (!phydev)
return -ENODEV;
static int ravb_config(struct udevice *dev)
{
struct ravb_priv *eth = dev_get_priv(dev);
- struct phy_device *phy;
+ struct phy_device *phy = eth->phydev;
u32 mask = ECMR_CHG_DM | ECMR_RE | ECMR_TE;
int ret;
ravb_mac_init(eth);
ravb_write_hwaddr(dev);
- /* Configure phy */
- ret = ravb_phy_config(dev);
- if (ret)
- return ret;
-
- phy = eth->phydev;
-
ret = phy_startup(phy);
if (ret)
return ret;
return 0;
}
-int ravb_start(struct udevice *dev)
+static int ravb_start(struct udevice *dev)
{
struct ravb_priv *eth = dev_get_priv(dev);
int ret;
- ret = clk_enable(ð->clk);
- if (ret)
- return ret;
-
ret = ravb_reset(dev);
if (ret)
goto err;
{
struct ravb_priv *eth = dev_get_priv(dev);
+ phy_shutdown(eth->phydev);
ravb_reset(dev);
- clk_disable(ð->clk);
}
static int ravb_probe(struct udevice *dev)
if (ret < 0)
goto err_mdio_alloc;
+ gpio_request_by_name(dev, "reset-gpios", 0, ð->reset_gpio,
+ GPIOD_IS_OUT);
+
mdiodev = mdio_alloc();
if (!mdiodev) {
ret = -ENOMEM;
eth->bus = miiphy_get_dev_by_name(dev->name);
+ /* Bring up PHY */
+ ret = clk_enable(ð->clk);
+ if (ret)
+ goto err_mdio_register;
+
+ ret = ravb_reset(dev);
+ if (ret)
+ goto err_mdio_reset;
+
+ ret = ravb_phy_config(dev);
+ if (ret)
+ goto err_mdio_reset;
+
return 0;
+err_mdio_reset:
+ clk_disable(ð->clk);
err_mdio_register:
mdio_free(mdiodev);
err_mdio_alloc:
{
struct ravb_priv *eth = dev_get_priv(dev);
+ clk_disable(ð->clk);
+
free(eth->phydev);
mdio_unregister(eth->bus);
mdio_free(eth->bus);
+ if (dm_gpio_is_valid(ð->reset_gpio))
+ dm_gpio_free(dev, ð->reset_gpio);
unmap_physmem(eth->iobase, MAP_NOCACHE);
return 0;
static const struct udevice_id ravb_ids[] = {
{ .compatible = "renesas,etheravb-r8a7795" },
{ .compatible = "renesas,etheravb-r8a7796" },
+ { .compatible = "renesas,etheravb-r8a77965" },
+ { .compatible = "renesas,etheravb-r8a77970" },
+ { .compatible = "renesas,etheravb-r8a77995" },
{ .compatible = "renesas,etheravb-rcar-gen3" },
{ }
};