driver/fsl_debug_server: Fix the DDR hide logic for LS2085a

[u-boot] / drivers / net / sh_eth.h

diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 09257590fdb78274382ab4b8608602fe4f8f1820..5cb520c63ec76c4d95bf5954cfc606868c9e0244 100644 (file)
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -51,8 +51,6 @@
 /* The size of the tx descriptor is determined by how much padding is used.
    4, 20, or 52 bytes of padding can be used */
 #define TX_DESC_PADDING        (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
-/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
-#define TX_DESC_SIZE   (12 + TX_DESC_PADDING)
 
 /* Tx descriptor. We always use 3 bytes of padding */
 struct tx_desc_s {
@@ -68,8 +66,6 @@ struct tx_desc_s {
 /* The size of the rx descriptor is determined by how much padding is used.
    4, 20, or 52 bytes of padding can be used */
 #define RX_DESC_PADDING        (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
-/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
-#define RX_DESC_SIZE           (12 + RX_DESC_PADDING)
 /* aligned cache line size */
 #define RX_BUF_ALIGNE_SIZE     (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
 
@@ -82,13 +78,13 @@ struct rx_desc_s {
 };
 
 struct sh_eth_info {
-       struct tx_desc_s *tx_desc_malloc;
+       struct tx_desc_s *tx_desc_alloc;
        struct tx_desc_s *tx_desc_base;
        struct tx_desc_s *tx_desc_cur;
-       struct rx_desc_s *rx_desc_malloc;
+       struct rx_desc_s *rx_desc_alloc;
        struct rx_desc_s *rx_desc_base;
        struct rx_desc_s *rx_desc_cur;
-       u8 *rx_buf_malloc;
+       u8 *rx_buf_alloc;
        u8 *rx_buf_base;
        u8 mac_addr[6];
        u8 phy_addr;
@@ -358,7 +354,8 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 #elif defined(CONFIG_R8A7740)
 #define SH_ETH_TYPE_GETHER
 #define BASE_IO_ADDR   0xE9A00000
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+       defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 #define SH_ETH_TYPE_ETHER
 #define BASE_IO_ADDR   0xEE700200
 #elif defined(CONFIG_R7S72100)
@@ -452,7 +449,6 @@ enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
 
 /* EESR */
 enum EESR_BIT {
-
 #if defined(SH_ETH_TYPE_ETHER)
        EESR_TWB  = 0x40000000,
 #else
@@ -477,7 +473,7 @@ enum EESR_BIT {
        EESR_CD   = 0x00000200, EESR_RTO  = 0x00000100,
        EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
        EESR_CELF = 0x00000020, EESR_RRF  = 0x00000010,
-       rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
+       EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
        EESR_PRE  = 0x00000002, EESR_CERF = 0x00000001,
 };
 
@@ -560,8 +556,8 @@ enum RECV_RST_BIT { RMCR_RST = 0x01, };
 /* ECMR */
 enum FELIC_MODE_BIT {
 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
-       ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000,
-       ECMR_RZPF = 0x00100000,
+       ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
+       ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
 #endif
        ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
        ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
@@ -570,15 +566,16 @@ enum FELIC_MODE_BIT {
        ECMR_PRM = 0x00000001,
 #ifdef CONFIG_CPU_SH7724
        ECMR_RTM = 0x00000010,
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+       defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
        ECMR_RTM = 0x00000004,
 #endif
 
 };
 
 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
-#define ECMR_CHG_DM    (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \
-                                               ECMR_TXF | ECMR_MCT)
+#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | \
+                       ECMR_RXF | ECMR_TXF | ECMR_MCT)
 #elif defined(SH_ETH_TYPE_ETHER)
 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
 #else