Add GPL-2.0+ SPDX-License-Identifier to source files

[u-boot] / drivers / net / sh_eth.h

diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 13003ec8a28167b0180a86de38ceb5bc5f7524c1..9ad800e4273e106c5d59ff5fa17f23ce95517856 100644 (file)
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -1,23 +1,11 @@
 /*
  * sh_eth.h - Driver for Renesas SuperH ethernet controler.
  *
- * Copyright (C) 2008, 2011 Renesas Solutions Corp.
- * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
+ * Copyright (C) 2008 - 2012 Renesas Solutions Corp.
+ * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu
  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
  *
- * This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <netdev.h>
@@ -25,6 +13,7 @@
 
 #define SHETHER_NAME "sh_eth"
 
+#if defined(CONFIG_SH)
 /* Malloc returns addresses in the P1 area (cacheable). However we need to
    use area P2 (non-cacheable) */
 #define ADDR_TO_P2(addr)       ((((int)(addr) & ~0xe0000000) | 0xa0000000))
@@ -35,6 +24,12 @@
 #else
 #define ADDR_TO_PHY(addr)      ((int)(addr) & ~0xe0000000)
 #endif
+#elif defined(CONFIG_ARM)
+#define inl            readl
+#define outl   writel
+#define ADDR_TO_PHY(addr)      ((int)(addr))
+#define ADDR_TO_P2(addr)       (addr)
+#endif /* defined(CONFIG_SH) */
 
 /* Number of supported ports */
 #define MAX_PORT_NUM   2
@@ -281,12 +276,20 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 #define SH_ETH_TYPE_GETHER
 #define BASE_IO_ADDR   0xfee00000
-#elif defined(CONFIG_CPU_SH7757)
+#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
+#if defined(CONFIG_SH_ETHER_USE_GETHER)
+#define SH_ETH_TYPE_GETHER
+#define BASE_IO_ADDR   0xfee00000
+#else
 #define SH_ETH_TYPE_ETHER
 #define BASE_IO_ADDR   0xfef00000
+#endif
 #elif defined(CONFIG_CPU_SH7724)
 #define SH_ETH_TYPE_ETHER
 #define BASE_IO_ADDR   0xA4600000
+#elif defined(CONFIG_R8A7740)
+#define SH_ETH_TYPE_GETHER
+#define BASE_IO_ADDR   0xE9A00000
 #endif
 
 /*
@@ -331,7 +334,11 @@ enum DMAC_T_BIT {
 
 /* GECMR */
 enum GECMR_BIT {
+#if defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
+       GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00,
+#else
        GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
+#endif
 };
 
 /* EDRRR*/