]> git.sur5r.net Git - u-boot/blobdiff - drivers/net/sun8i_emac.c
libfdt: Bring in upstream stringlist functions
[u-boot] / drivers / net / sun8i_emac.c
index 4bed50d66808c2c505c0f9d0cff51577952a5602..91570a29106f6d5ccd8ba80be7c976d097c8e8d9 100644 (file)
 #include <miiphy.h>
 #include <net.h>
 
-#define SCTL_EMAC_TX_CLK_SRC_MII       BIT(0)
-#define SCTL_EMAC_EPIT_MII             BIT(2)
-#define SCTL_EMAC_CLK_SEL              BIT(18) /* 25 Mhz */
-
 #define MDIO_CMD_MII_BUSY              BIT(0)
 #define MDIO_CMD_MII_WRITE             BIT(1)
 
 
 #define CONFIG_TX_DESCR_NUM    32
 #define CONFIG_RX_DESCR_NUM    32
-#define CONFIG_ETH_BUFSIZE     2024
+#define CONFIG_ETH_BUFSIZE     2048 /* Note must be dma aligned */
+
+/*
+ * The datasheet says that each descriptor can transfers up to 4096 bytes
+ * But later, the register documentation reduces that value to 2048,
+ * using 2048 cause strange behaviours and even BSP driver use 2047
+ */
+#define CONFIG_ETH_RXSIZE      2044 /* Note must fit in ETH_BUFSIZE */
 
 #define TX_TOTAL_BUFSIZE       (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
 #define RX_TOTAL_BUFSIZE       (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
@@ -328,7 +331,7 @@ static void rx_descs_init(struct emac_eth_dev *priv)
                desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]
                        ;
                desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
-               desc_p->st |= CONFIG_ETH_BUFSIZE;
+               desc_p->st |= CONFIG_ETH_RXSIZE;
                desc_p->status = BIT(31);
        }
 
@@ -453,8 +456,9 @@ static int parse_phy_pins(struct udevice *dev)
        for (i = 0; ; i++) {
                int pin;
 
-               if (fdt_get_string_index(gd->fdt_blob, offset,
-                                        "allwinner,pins", i, &pin_name))
+               pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
+                                        "allwinner,pins", i, NULL);
+               if (!pin_name)
                        break;
                if (pin_name[0] != 'P')
                        continue;
@@ -510,7 +514,7 @@ static int _sun8i_eth_recv(struct emac_eth_dev *priv, uchar **packetp)
                                        roundup(data_end,
                                                ARCH_DMA_MINALIGN));
                if (good_packet) {
-                       if (length > CONFIG_ETH_BUFSIZE) {
+                       if (length > CONFIG_ETH_RXSIZE) {
                                printf("Received packet is too big (len=%d)\n",
                                       length);
                                return -EMSGSIZE;
@@ -589,9 +593,6 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
                /* Set clock gating for ephy */
                setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY));
 
-               /* Set Tx clock source as MII with rate 25 MZ */
-               setbits_le32(priv->sysctl_reg, SCTL_EMAC_TX_CLK_SRC_MII |
-                               SCTL_EMAC_EPIT_MII | SCTL_EMAC_CLK_SEL);
                /* Deassert EPHY */
                setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY));
        }
@@ -599,9 +600,6 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
        /* Set clock gating for emac */
        setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
 
-       /* Set EMAC clock */
-       setbits_le32(&ccm->axi_gate, (BIT(1) | BIT(0)));
-
        /* De-assert EMAC */
        setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
 }
@@ -696,12 +694,11 @@ static int sun8i_emac_eth_probe(struct udevice *dev)
        priv->mac_reg = (void *)pdata->iobase;
 
        sun8i_emac_board_setup(priv);
+       sun8i_emac_set_syscon(priv);
 
        sun8i_mdio_init(dev->name, priv);
        priv->bus = miiphy_get_dev_by_name(dev->name);
 
-       sun8i_emac_set_syscon(priv);
-
        return sun8i_phy_init(priv, dev);
 }