+// SPDX-License-Identifier: GPL-2.0+
/*
* Freescale Three Speed Ethernet Controller driver
*
* Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
* (C) Copyright 2003, Motorola, Inc.
* author Andy Fleming
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <common.h>
+#include <dm.h>
#include <malloc.h>
#include <net.h>
#include <command.h>
#include <tsec.h>
#include <fsl_mdio.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/processor.h>
#include <asm/io.h>
-DECLARE_GLOBAL_DATA_PTR;
-
+#ifndef CONFIG_DM_ETH
/* Default initializations for TSEC controllers. */
static struct tsec_info_struct tsec_info[] = {
STD_TSEC_INFO(4), /* TSEC4 */
#endif
};
+#endif /* CONFIG_DM_ETH */
#define TBIANA_SETTINGS ( \
TBIANA_ASYMMETRIC_PAUSE \
* to the register offset used for external PHY accesses
*/
tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
- 0, TBI_ANA, TBIANA_SETTINGS);
+ 0, TBI_ANA, TBIANA_SETTINGS);
tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
- 0, TBI_TBICON, TBICON_CLK_SELECT);
+ 0, TBI_TBICON, TBICON_CLK_SELECT);
tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
- 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
+ 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
}
#ifdef CONFIG_MCAST_TFTP
* for PowerPC (tm) is usually the case) in the register holds
* the entry.
*/
+#ifndef CONFIG_DM_ETH
static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
+#else
+static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int set)
+#endif
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
struct tsec __iomem *regs = priv->regs;
whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
- value = 1 << (31-whichbit);
+ value = BIT(31 - whichbit);
if (set)
setbits_be32(®s->hash.gaddr0 + whichreg, value);
out_be32(®s->attr, ATTR_INIT_SETTINGS);
out_be32(®s->attreli, ATTRELI_INIT_SETTINGS);
-
}
/*
out_be32(®s->maccfg2, maccfg2);
printf("Speed: %d, %s duplex%s\n", phydev->speed,
- (phydev->duplex) ? "full" : "half",
- (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
+ (phydev->duplex) ? "full" : "half",
+ (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
}
/*
* do the same. Presumably, this would be zero if there were no
* errors
*/
+#ifndef CONFIG_DM_ETH
static int tsec_send(struct eth_device *dev, void *packet, int length)
+#else
+static int tsec_send(struct udevice *dev, void *packet, int length)
+#endif
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
struct tsec __iomem *regs = priv->regs;
- uint16_t status;
+ u16 status;
int result = 0;
int i;
return result;
}
+#ifndef CONFIG_DM_ETH
static int tsec_recv(struct eth_device *dev)
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
int length = in_be16(&priv->rxbd[priv->rx_idx].length);
- uint16_t status = in_be16(&priv->rxbd[priv->rx_idx].status);
+ u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
uchar *packet = net_rx_packets[priv->rx_idx];
/* Send the packet up if there were no errors */
return -1;
}
+#else
+static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct tsec_private *priv = (struct tsec_private *)dev->priv;
+ struct tsec __iomem *regs = priv->regs;
+ int ret = -1;
+
+ if (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
+ int length = in_be16(&priv->rxbd[priv->rx_idx].length);
+ u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
+ u32 buf;
+
+ /* Send the packet up if there were no errors */
+ if (!(status & RXBD_STATS)) {
+ buf = in_be32(&priv->rxbd[priv->rx_idx].bufptr);
+ *packetp = (uchar *)buf;
+ ret = length - 4;
+ } else {
+ printf("Got error %x\n", (status & RXBD_STATS));
+ }
+ }
+
+ if (in_be32(®s->ievent) & IEVENT_BSY) {
+ out_be32(®s->ievent, IEVENT_BSY);
+ out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
+ }
+
+ return ret;
+}
+
+static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct tsec_private *priv = (struct tsec_private *)dev->priv;
+ u16 status;
+
+ out_be16(&priv->rxbd[priv->rx_idx].length, 0);
+
+ status = RXBD_EMPTY;
+ /* Set the wrap bit if this is the last element in the list */
+ if ((priv->rx_idx + 1) == PKTBUFSRX)
+ status |= RXBD_WRAP;
+ out_be16(&priv->rxbd[priv->rx_idx].status, status);
+
+ priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
+
+ return 0;
+}
+#endif
/* Stop the interface */
+#ifndef CONFIG_DM_ETH
static void tsec_halt(struct eth_device *dev)
+#else
+static void tsec_halt(struct udevice *dev)
+#endif
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
struct tsec __iomem *regs = priv->regs;
* of the eTSEC port initialization sequence,
* the eTSEC Rx logic may not be properly initialized.
*/
-void redundant_init(struct eth_device *dev)
+void redundant_init(struct tsec_private *priv)
{
- struct tsec_private *priv = dev->priv;
struct tsec __iomem *regs = priv->regs;
uint t, count = 0;
int fail = 1;
clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
do {
- uint16_t status;
- tsec_send(dev, (void *)pkt, sizeof(pkt));
+ u16 status;
+
+ tsec_send(priv->dev, (void *)pkt, sizeof(pkt));
/* Wait for buffer to be received */
for (t = 0;
in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY;
t++) {
if (t >= 10 * TOUT_LOOP) {
- printf("%s: tsec: rx error\n", dev->name);
+ printf("%s: tsec: rx error\n", priv->dev->name);
break;
}
}
* Set up the buffers and their descriptors, and bring up the
* interface
*/
-static void startup_tsec(struct eth_device *dev)
+static void startup_tsec(struct tsec_private *priv)
{
- struct tsec_private *priv = (struct tsec_private *)dev->priv;
struct tsec __iomem *regs = priv->regs;
- uint16_t status;
+ u16 status;
int i;
/* reset the indices to zero */
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
svr = get_svr();
if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
- redundant_init(dev);
+ redundant_init(priv);
#endif
/* Enable Transmit and Receive */
setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
* that it returns success if the link is up, failure otherwise.
* This allows U-Boot to find the first active controller.
*/
-static int tsec_init(struct eth_device *dev, bd_t * bd)
+#ifndef CONFIG_DM_ETH
+static int tsec_init(struct eth_device *dev, bd_t *bd)
+#else
+static int tsec_init(struct udevice *dev)
+#endif
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
+#ifdef CONFIG_DM_ETH
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+#endif
struct tsec __iomem *regs = priv->regs;
u32 tempval;
int ret;
* order (BE), MACnADDR1 is set to 0xCDAB7856 and
* MACnADDR2 is set to 0x34120000.
*/
+#ifndef CONFIG_DM_ETH
tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) |
(dev->enetaddr[3] << 8) | dev->enetaddr[2];
+#else
+ tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) |
+ (pdata->enetaddr[3] << 8) | pdata->enetaddr[2];
+#endif
out_be32(®s->macstnaddr1, tempval);
+#ifndef CONFIG_DM_ETH
tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16);
+#else
+ tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16);
+#endif
out_be32(®s->macstnaddr2, tempval);
init_registers(regs);
/* Ready the device for tx/rx */
- startup_tsec(dev);
+ startup_tsec(priv);
/* Start up the PHY */
ret = phy_startup(priv->phydev);
}
if (ecntrl & ECNTRL_REDUCED_MODE) {
+ phy_interface_t interface;
+
if (ecntrl & ECNTRL_REDUCED_MII_MODE)
return PHY_INTERFACE_MODE_RMII;
- else {
- phy_interface_t interface = priv->interface;
-
- /*
- * This isn't autodetected, so it must
- * be set by the platform code.
- */
- if ((interface == PHY_INTERFACE_MODE_RGMII_ID) ||
- (interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
- (interface == PHY_INTERFACE_MODE_RGMII_RXID))
- return interface;
-
- return PHY_INTERFACE_MODE_RGMII;
- }
+
+ interface = priv->interface;
+
+ /*
+ * This isn't autodetected, so it must
+ * be set by the platform code.
+ */
+ if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ interface == PHY_INTERFACE_MODE_RGMII_TXID ||
+ interface == PHY_INTERFACE_MODE_RGMII_RXID)
+ return interface;
+
+ return PHY_INTERFACE_MODE_RGMII;
}
if (priv->flags & TSEC_GIGABIT)
* properly. If the PHY is not recognized, then return 0
* (failure). Otherwise, return 1
*/
-static int init_phy(struct eth_device *dev)
+static int init_phy(struct tsec_private *priv)
{
- struct tsec_private *priv = (struct tsec_private *)dev->priv;
struct phy_device *phydev;
struct tsec __iomem *regs = priv->regs;
u32 supported = (SUPPORTED_10baseT_Half |
supported |= SUPPORTED_1000baseT_Full;
/* Assign a Physical address to the TBI */
- out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
+ out_be32(®s->tbipa, priv->tbiaddr);
priv->interface = tsec_get_interface(priv);
if (priv->interface == PHY_INTERFACE_MODE_SGMII)
tsec_configure_serdes(priv);
- phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
+ phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
+ priv->interface);
if (!phydev)
return 0;
return 1;
}
+#ifndef CONFIG_DM_ETH
/*
* Initialize device structure. Returns success if PHY
* initialization succeeded (i.e. if it recognizes the PHY)
int i;
struct tsec_private *priv;
- dev = (struct eth_device *)malloc(sizeof *dev);
+ dev = (struct eth_device *)malloc(sizeof(*dev));
- if (NULL == dev)
+ if (!dev)
return 0;
- memset(dev, 0, sizeof *dev);
+ memset(dev, 0, sizeof(*dev));
priv = (struct tsec_private *)malloc(sizeof(*priv));
- if (NULL == priv)
+ if (!priv) {
+ free(dev);
return 0;
+ }
priv->regs = tsec_info->regs;
priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
priv->phyaddr = tsec_info->phyaddr;
+ priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
priv->flags = tsec_info->flags;
- sprintf(dev->name, tsec_info->devname);
+ strcpy(dev->name, tsec_info->devname);
priv->interface = tsec_info->interface;
priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
+ priv->dev = dev;
dev->iobase = 0;
dev->priv = priv;
dev->init = tsec_init;
clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
/* Try to initialize PHY here, and return */
- return init_phy(dev);
+ return init_phy(priv);
}
/*
int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
{
int i;
- int ret, count = 0;
+ int count = 0;
for (i = 0; i < num; i++) {
- ret = tsec_initialize(bis, &tsecs[i]);
+ int ret = tsec_initialize(bis, &tsecs[i]);
+
if (ret > 0)
count += ret;
}
return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
}
+#else /* CONFIG_DM_ETH */
+int tsec_probe(struct udevice *dev)
+{
+ struct tsec_private *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct fsl_pq_mdio_info mdio_info;
+ struct ofnode_phandle_args phandle_args;
+ ofnode parent;
+ const char *phy_mode;
+ int ret;
+
+ pdata->iobase = (phys_addr_t)dev_read_addr(dev);
+ priv->regs = (struct tsec *)pdata->iobase;
+
+ if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+ &phandle_args)) {
+ debug("phy-handle does not exist under tsec %s\n", dev->name);
+ return -ENOENT;
+ } else {
+ int reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
+
+ priv->phyaddr = reg;
+ }
+
+ parent = ofnode_get_parent(phandle_args.node);
+ if (ofnode_valid(parent)) {
+ int reg = ofnode_get_addr_index(parent, 0);
+
+ priv->phyregs_sgmii = (struct tsec_mii_mng *)reg;
+ } else {
+ debug("No parent node for PHY?\n");
+ return -ENOENT;
+ }
+
+ if (dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
+ &phandle_args)) {
+ priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
+ } else {
+ int reg = ofnode_read_u32_default(phandle_args.node, "reg",
+ CONFIG_SYS_TBIPA_VALUE);
+ priv->tbiaddr = reg;
+ }
+
+ phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
+ if (phy_mode)
+ pdata->phy_interface = phy_get_interface_by_name(phy_mode);
+ if (pdata->phy_interface == -1) {
+ debug("Invalid PHY interface '%s'\n", phy_mode);
+ return -EINVAL;
+ }
+ priv->interface = pdata->phy_interface;
+
+ /* Initialize flags */
+ priv->flags = TSEC_GIGABIT;
+ if (priv->interface == PHY_INTERFACE_MODE_SGMII)
+ priv->flags |= TSEC_SGMII;
+
+ mdio_info.regs = priv->phyregs_sgmii;
+ mdio_info.name = (char *)dev->name;
+ ret = fsl_pq_mdio_init(NULL, &mdio_info);
+ if (ret)
+ return ret;
+
+ /* Reset the MAC */
+ setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
+ udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
+ clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
+
+ priv->dev = dev;
+ priv->bus = miiphy_get_dev_by_name(dev->name);
+
+ /* Try to initialize PHY here, and return */
+ return !init_phy(priv);
+}
+
+int tsec_remove(struct udevice *dev)
+{
+ struct tsec_private *priv = dev->priv;
+
+ free(priv->phydev);
+ mdio_unregister(priv->bus);
+ mdio_free(priv->bus);
+
+ return 0;
+}
+
+static const struct eth_ops tsec_ops = {
+ .start = tsec_init,
+ .send = tsec_send,
+ .recv = tsec_recv,
+ .free_pkt = tsec_free_pkt,
+ .stop = tsec_halt,
+#ifdef CONFIG_MCAST_TFTP
+ .mcast = tsec_mcast_addr,
+#endif
+};
+
+static const struct udevice_id tsec_ids[] = {
+ { .compatible = "fsl,tsec" },
+ { }
+};
+
+U_BOOT_DRIVER(eth_tsec) = {
+ .name = "tsec",
+ .id = UCLASS_ETH,
+ .of_match = tsec_ids,
+ .probe = tsec_probe,
+ .remove = tsec_remove,
+ .ops = &tsec_ops,
+ .priv_auto_alloc_size = sizeof(struct tsec_private),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif /* CONFIG_DM_ETH */
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