net: zynq_gem: Dont run any phy detection logic for GMII case

[u-boot] / drivers / net / zynq_gem.c

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index f3d6727a9d2939ea949a62c1c2255284809243d2..1390c36c6141c610a47dfddd2e0e1164dad5888f 100644 (file)
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -182,6 +182,7 @@ struct zynq_gem_priv {
        int phy_of_handle;
        struct mii_dev *bus;
        struct clk clk;
+       bool int_pcs;
 };
 
 static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
@@ -191,8 +192,8 @@ static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
        struct zynq_gem_regs *regs = priv->iobase;
        int err;
 
-       err = wait_for_bit(__func__, &regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
-                           true, 20000, true);
+       err = wait_for_bit_le32(&regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
+                               true, 20000, false);
        if (err)
                return err;
 
@@ -204,8 +205,8 @@ static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
        /* Write mgtcr and wait for completion */
        writel(mgtcr, &regs->phymntnc);
 
-       err = wait_for_bit(__func__, &regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
-                           true, 20000, true);
+       err = wait_for_bit_le32(&regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
+                               true, 20000, false);
        if (err)
                return err;
 
@@ -324,7 +325,8 @@ static int zynq_phy_init(struct udevice *dev)
        /* Enable only MDIO bus */
        writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, &regs->nwctrl);
 
-       if (priv->interface != PHY_INTERFACE_MODE_SGMII) {
+       if ((priv->interface != PHY_INTERFACE_MODE_SGMII) &&
+           (priv->interface != PHY_INTERFACE_MODE_GMII)) {
                ret = phy_detection(dev);
                if (ret) {
                        printf("GEM PHY init failed\n");
@@ -407,10 +409,6 @@ static int zynq_gem_init(struct udevice *dev)
                dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
                                ZYNQ_GEM_RXBUF_NEW_MASK;
                dummy_rx_bd->status = 0;
-               flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd +
-                                  sizeof(dummy_tx_bd));
-               flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd +
-                                  sizeof(dummy_rx_bd));
 
                writel((ulong)dummy_tx_bd, &regs->transmit_q1_ptr);
                writel((ulong)dummy_rx_bd, &regs->receive_q1_ptr);
@@ -429,7 +427,12 @@ static int zynq_gem_init(struct udevice *dev)
 
        nwconfig = ZYNQ_GEM_NWCFG_INIT;
 
-       if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
+       /*
+        * Set SGMII enable PCS selection only if internal PCS/PMA
+        * core is used and interface is SGMII.
+        */
+       if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
+           priv->int_pcs) {
                nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
                            ZYNQ_GEM_NWCFG_PCS_SEL;
 #ifdef CONFIG_ARM64
@@ -512,8 +515,8 @@ static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
        if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
                printf("TX buffers exhausted in mid frame\n");
 
-       return wait_for_bit(__func__, &regs->txsr, ZYNQ_GEM_TSR_DONE,
-                           true, 20000, true);
+       return wait_for_bit_le32(&regs->txsr, ZYNQ_GEM_TSR_DONE,
+                                true, 20000, true);
 }
 
 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
@@ -701,6 +704,9 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
        }
        priv->interface = pdata->phy_interface;
 
+       priv->int_pcs = fdtdec_get_bool(gd->fdt_blob, node,
+                                       "is-internal-pcspma");
+
        printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
               priv->phyaddr, phy_string_for_interface(priv->interface));