net: designware: Add phy supply support

[u-boot] / drivers / net / zynq_gem.c

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index d3c33e801d62862ea9608815f08d3c796b91a28e..1bb7fa576f581903a6e12c8b129dc7d9c9cd3131 100644 (file)
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -181,9 +181,7 @@ struct zynq_gem_priv {
        struct phy_device *phydev;
        int phy_of_handle;
        struct mii_dev *bus;
-#ifdef CONFIG_CLK_ZYNQMP
        struct clk clk;
-#endif
 };
 
 static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
@@ -339,7 +337,7 @@ static int zynq_phy_init(struct udevice *dev)
        if (!priv->phydev)
                return -ENODEV;
 
-       priv->phydev->supported = supported | ADVERTISED_Pause |
+       priv->phydev->supported &= supported | ADVERTISED_Pause |
                                  ADVERTISED_Asym_Pause;
        priv->phydev->advertising = priv->phydev->supported;
 
@@ -456,14 +454,17 @@ static int zynq_gem_init(struct udevice *dev)
                break;
        }
 
-#ifndef CONFIG_CLK_ZYNQMP
-       zynq_slcr_gem_clk_setup((ulong)priv->iobase !=
-                               ZYNQ_GEM_BASEADDR0, clk_rate);
-#else
        ret = clk_set_rate(&priv->clk, clk_rate);
-       if (IS_ERR_VALUE(ret))
-               return -1;
-#endif
+       if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
+               dev_err(dev, "failed to set tx clock rate\n");
+               return ret;
+       }
+
+       ret = clk_enable(&priv->clk);
+       if (ret && ret != -ENOSYS) {
+               dev_err(dev, "failed to enable tx clock\n");
+               return ret;
+       }
 
        setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
                                        ZYNQ_GEM_NWCTRL_TXEN_MASK);
@@ -636,13 +637,11 @@ static int zynq_gem_probe(struct udevice *dev)
        priv->tx_bd = (struct emac_bd *)bd_space;
        priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
 
-#ifdef CONFIG_CLK_ZYNQMP
        ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
        if (ret < 0) {
                dev_err(dev, "failed to get clock\n");
                return -EINVAL;
        }
-#endif
 
        priv->bus = mdio_alloc();
        priv->bus->read = zynq_gem_miiphy_read;
@@ -684,7 +683,7 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
        int node = dev_of_offset(dev);
        const char *phy_mode;
 
-       pdata->iobase = (phys_addr_t)dev_get_addr(dev);
+       pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
        priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
        /* Hardcode for now */
        priv->phyaddr = -1;