i2c: switch from AT91 legacy to ATMEL legacy

[u-boot] / drivers / net / zynq_gem.c

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 2d717e91034e5924b51a8dee7dd019df2d466ccd..236a75311f3a9d7a1e2473362814f2c2b9a02071 100644 (file)
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -6,23 +6,7 @@
  * Based on Xilinx gmac driver:
  * (C) Copyright 2011 Xilinx
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -33,6 +17,7 @@
 #include <phy.h>
 #include <miiphy.h>
 #include <watchdog.h>
+#include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 
 #if !defined(CONFIG_PHYLIB)
@@ -94,6 +79,17 @@
                                        ZYNQ_GEM_DMACR_TXSIZE | \
                                        ZYNQ_GEM_DMACR_RXBUF)
 
+/* Use MII register 1 (MII status register) to detect PHY */
+#define PHY_DETECT_REG  1
+
+/* Mask used to verify certain PHY features (or register contents)
+ * in the register above:
+ *  0x1000: 10Mbps full duplex support
+ *  0x0800: 10Mbps half duplex support
+ *  0x0008: Auto-negotiation support
+ */
+#define PHY_DETECT_MASK 0x1808
+
 /* Device registers */
 struct zynq_gem_regs {
        u32 nwctrl; /* Network Control reg */
@@ -136,6 +132,7 @@ struct zynq_gem_priv {
        u32 rxbd_current;
        u32 rx_first_buf;
        int phyaddr;
+       u32 emio;
        int init;
        struct phy_device *phydev;
        struct mii_dev *bus;
@@ -199,6 +196,44 @@ static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data)
                                ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
 }
 
+static void phy_detection(struct eth_device *dev)
+{
+       int i;
+       u16 phyreg;
+       struct zynq_gem_priv *priv = dev->priv;
+
+       if (priv->phyaddr != -1) {
+               phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg);
+               if ((phyreg != 0xFFFF) &&
+                   ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
+                       /* Found a valid PHY address */
+                       debug("Default phy address %d is valid\n",
+                             priv->phyaddr);
+                       return;
+               } else {
+                       debug("PHY address is not setup correctly %d\n",
+                             priv->phyaddr);
+                       priv->phyaddr = -1;
+               }
+       }
+
+       debug("detecting phy address\n");
+       if (priv->phyaddr == -1) {
+               /* detect the PHY address */
+               for (i = 31; i >= 0; i--) {
+                       phyread(dev, i, PHY_DETECT_REG, &phyreg);
+                       if ((phyreg != 0xFFFF) &&
+                           ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
+                               /* Found a valid PHY address */
+                               priv->phyaddr = i;
+                               debug("Found valid phy address, %d\n", i);
+                               return;
+                       }
+               }
+       }
+       printf("PHY is not detected\n");
+}
+
 static int zynq_gem_setup_mac(struct eth_device *dev)
 {
        u32 i, macaddrlow, macaddrhigh;
@@ -288,6 +323,8 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
                priv->init++;
        }
 
+       phy_detection(dev);
+
        /* interface - look at tsec */
        phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0);
 
@@ -317,8 +354,11 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
                clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
                break;
        }
-       /* FIXME maybe better to define gem address in hardware.h */
-       zynq_slcr_gem_clk_setup(dev->iobase != 0xE000B000, rclk, clk);
+
+       /* Change the rclk and clk only not using EMIO interface */
+       if (!priv->emio)
+               zynq_slcr_gem_clk_setup(dev->iobase !=
+                                       ZYNQ_GEM_BASEADDR0, rclk, clk);
 
        setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
                                        ZYNQ_GEM_NWCTRL_TXEN_MASK);
@@ -427,7 +467,7 @@ static int zynq_gem_miiphy_write(const char *devname, uchar addr,
        return phywrite(dev, addr, reg, val);
 }
 
-int zynq_gem_initialize(bd_t *bis, int base_addr)
+int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio)
 {
        struct eth_device *dev;
        struct zynq_gem_priv *priv;
@@ -443,11 +483,8 @@ int zynq_gem_initialize(bd_t *bis, int base_addr)
        }
        priv = dev->priv;
 
-#ifdef CONFIG_PHY_ADDR
-       priv->phyaddr = CONFIG_PHY_ADDR;
-#else
-       priv->phyaddr = -1;
-#endif
+       priv->phyaddr = phy_addr;
+       priv->emio = emio;
 
        sprintf(dev->name, "Gem.%x", base_addr);