pci: Set PCI_COMMAND_IO bit for VGA device

[u-boot] / drivers / net / zynq_gem.c

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index f4c2252d0c14a2f9dc1c4f67ab185d4ac10366e2..9175d2cae8f75676009ea0b0a3d9bfe74c704dae 100644 (file)
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -163,7 +163,7 @@ struct zynq_gem_priv {
 static inline int mdio_wait(struct eth_device *dev)
 {
        struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
-       u32 timeout = 200;
+       u32 timeout = 20000;
 
        /* Wait till MDIO interface is ready to accept a new transaction. */
        while (--timeout) {
@@ -403,7 +403,8 @@ static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
 
        priv->tx_bd->addr = (u32)ptr;
        priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
-                               ZYNQ_GEM_TXBUF_LAST_MASK;
+                              ZYNQ_GEM_TXBUF_LAST_MASK |
+                              ZYNQ_GEM_TXBUF_WRAP_MASK;
 
        addr = (u32) ptr;
        addr &= ~(ARCH_DMA_MINALIGN - 1);
@@ -552,7 +553,7 @@ int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
        return 1;
 }
 
-#ifdef CONFIG_OF_CONTROL
+#if CONFIG_IS_ENABLED(OF_CONTROL)
 int zynq_gem_of_init(const void *blob)
 {
        int offset = 0;