dwc2 USB controller hangs with lan78xx

[u-boot] / drivers / net / zynq_gem.c

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 2cc49bca922a1f0896a9e6368813df77313b0661..a817f2e5d69ba247430a1f6e7316d0341d4d7941 100644 (file)
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2011 Michal Simek
  *
@@ -5,8 +6,6 @@
  *
  * Based on Xilinx gmac driver:
  * (C) Copyright 2011 Xilinx
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <clk.h>
@@ -182,10 +181,11 @@ struct zynq_gem_priv {
        int phy_of_handle;
        struct mii_dev *bus;
        struct clk clk;
+       u32 max_speed;
        bool int_pcs;
 };
 
-static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
+static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
                        u32 op, u16 *data)
 {
        u32 mgtcr;
@@ -216,10 +216,10 @@ static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
        return 0;
 }
 
-static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr,
+static int phyread(struct zynq_gem_priv *priv, u32 phy_addr,
                   u32 regnum, u16 *val)
 {
-       u32 ret;
+       int ret;
 
        ret = phy_setup_op(priv, phy_addr, regnum,
                           ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
@@ -231,7 +231,7 @@ static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr,
        return ret;
 }
 
-static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
+static int phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
                    u32 regnum, u16 data)
 {
        debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
@@ -244,7 +244,7 @@ static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
 static int phy_detection(struct udevice *dev)
 {
        int i;
-       u16 phyreg;
+       u16 phyreg = 0;
        struct zynq_gem_priv *priv = dev->priv;
 
        if (priv->phyaddr != -1) {
@@ -325,7 +325,8 @@ static int zynq_phy_init(struct udevice *dev)
        /* Enable only MDIO bus */
        writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, &regs->nwctrl);
 
-       if (priv->interface != PHY_INTERFACE_MODE_SGMII) {
+       if ((priv->interface != PHY_INTERFACE_MODE_SGMII) &&
+           (priv->interface != PHY_INTERFACE_MODE_GMII)) {
                ret = phy_detection(dev);
                if (ret) {
                        printf("GEM PHY init failed\n");
@@ -340,6 +341,12 @@ static int zynq_phy_init(struct udevice *dev)
 
        priv->phydev->supported &= supported | ADVERTISED_Pause |
                                  ADVERTISED_Asym_Pause;
+       if (priv->max_speed) {
+               ret = phy_set_supported(priv->phydev, priv->max_speed);
+               if (ret)
+                       return ret;
+       }
+
        priv->phydev->advertising = priv->phydev->supported;
 
        if (priv->phy_of_handle > 0)
@@ -626,10 +633,16 @@ static int zynq_gem_probe(struct udevice *dev)
 
        /* Align rxbuffers to ARCH_DMA_MINALIGN */
        priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
+       if (!priv->rxbuffers)
+               return -ENOMEM;
+
        memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
 
        /* Align bd_space to MMU_SECTION_SHIFT */
        bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
+       if (!bd_space)
+               return -ENOMEM;
+
        mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
                                        BD_SPACE, DCACHE_OFF);
 
@@ -703,6 +716,8 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
        }
        priv->interface = pdata->phy_interface;
 
+       priv->max_speed = fdtdec_get_uint(gd->fdt_blob, priv->phy_of_handle,
+                                         "max-speed", SPEED_1000);
        priv->int_pcs = fdtdec_get_bool(gd->fdt_blob, node,
                                        "is-internal-pcspma");