+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2011 Michal Simek
*
*
* Based on Xilinx gmac driver:
* (C) Copyright 2011 Xilinx
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <clk.h>
bool int_pcs;
};
-static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
+static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
u32 op, u16 *data)
{
u32 mgtcr;
return 0;
}
-static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr,
+static int phyread(struct zynq_gem_priv *priv, u32 phy_addr,
u32 regnum, u16 *val)
{
- u32 ret;
+ int ret;
ret = phy_setup_op(priv, phy_addr, regnum,
ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
return ret;
}
-static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
+static int phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
u32 regnum, u16 data)
{
debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
static int phy_detection(struct udevice *dev)
{
int i;
- u16 phyreg;
+ u16 phyreg = 0;
struct zynq_gem_priv *priv = dev->priv;
if (priv->phyaddr != -1) {
{
struct zynq_gem_priv *priv = bus->priv;
int ret;
- u16 val;
+ u16 val = 0;
ret = phyread(priv, addr, reg, &val);
debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret);
/* Align rxbuffers to ARCH_DMA_MINALIGN */
priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
+ if (!priv->rxbuffers)
+ return -ENOMEM;
+
memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
/* Align bd_space to MMU_SECTION_SHIFT */
bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
+ if (!bd_space)
+ return -ENOMEM;
+
mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
BD_SPACE, DCACHE_OFF);