nvme: Use macros to access NVMe queues

[u-boot] / drivers / nvme / nvme.c

diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index 151fe92479ab8196d7f9119f627ac0ea60991272..868ff45cee6c6d4f15a585b001fca3a091b10ee1 100644 (file)
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -23,6 +23,12 @@ struct nvme_info *nvme_info;
 #define IO_TIMEOUT             30
 #define MAX_PRP_POOL           512
 
+enum nvme_queue_id {
+       NVME_ADMIN_Q,
+       NVME_IO_Q,
+       NVME_Q_NUM,
+};
+
 /*
  * An NVM Express queue. Each device has at least two (one for admin
  * commands and one for I/O commands).
@@ -47,11 +53,19 @@ struct nvme_queue {
 static int nvme_wait_ready(struct nvme_dev *dev, bool enabled)
 {
        u32 bit = enabled ? NVME_CSTS_RDY : 0;
+       int timeout;
+       ulong start;
 
-       while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit)
-               udelay(10000);
+       /* Timeout field in the CAP register is in 500 millisecond units */
+       timeout = NVME_CAP_TIMEOUT(dev->cap) * 500;
 
-       return 0;
+       start = get_timer(0);
+       while (get_timer(start) < timeout) {
+               if ((readl(&dev->bar->csts) & NVME_CSTS_RDY) == bit)
+                       return 0;
+       }
+
+       return -ETIME;
 }
 
 static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2,
@@ -201,7 +215,8 @@ static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
                                 u32 *result)
 {
-       return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
+       return nvme_submit_sync_cmd(dev->queues[NVME_ADMIN_Q], cmd,
+                                   result, ADMIN_TIMEOUT);
 }
 
 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev,
@@ -318,7 +333,7 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev)
 {
        int result;
        u32 aqa;
-       u64 cap = nvme_readq(&dev->bar->cap);
+       u64 cap = dev->cap;
        struct nvme_queue *nvmeq;
        /* most architectures use 4KB as the page size */
        unsigned page_shift = 12;
@@ -341,7 +356,7 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev)
        if (result < 0)
                return result;
 
-       nvmeq = dev->queues[0];
+       nvmeq = dev->queues[NVME_ADMIN_Q];
        if (!nvmeq) {
                nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
                if (!nvmeq)
@@ -369,7 +384,7 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev)
 
        nvmeq->cq_vector = 0;
 
-       nvme_init_queue(dev->queues[0], 0);
+       nvme_init_queue(dev->queues[NVME_ADMIN_Q], 0);
 
        return result;
 
@@ -431,7 +446,7 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid,
                c.identify.prp2 = 0;
        } else {
                dma_addr += (page_size - offset);
-               c.identify.prp2 = dma_addr;
+               c.identify.prp2 = cpu_to_le64(dma_addr);
        }
 
        c.identify.cns = cpu_to_le32(cns);
@@ -547,10 +562,9 @@ static int nvme_setup_io_queues(struct nvme_dev *dev)
 
 static int nvme_get_info_from_identify(struct nvme_dev *dev)
 {
-       u16 vendor, device;
        struct nvme_id_ctrl buf, *ctrl = &buf;
        int ret;
-       int shift = NVME_CAP_MPSMIN(nvme_readq(&dev->bar->cap)) + 12;
+       int shift = NVME_CAP_MPSMIN(dev->cap) + 12;
 
        ret = nvme_identify(dev, 0, 1, (dma_addr_t)ctrl);
        if (ret)
@@ -585,22 +599,6 @@ static int nvme_get_info_from_identify(struct nvme_dev *dev)
                dev->max_transfer_shift = 20;
        }
 
-       /* Apply quirk stuff */
-       dm_pci_read_config16(dev->pdev, PCI_VENDOR_ID, &vendor);
-       dm_pci_read_config16(dev->pdev, PCI_DEVICE_ID, &device);
-       if ((vendor == PCI_VENDOR_ID_INTEL) &&
-           (device == 0x0953) && ctrl->vs[3]) {
-               unsigned int max_transfer_shift;
-               dev->stripe_size = (ctrl->vs[3] + shift);
-               max_transfer_shift = (ctrl->vs[3] + 18);
-               if (dev->max_transfer_shift) {
-                       dev->max_transfer_shift = min(max_transfer_shift,
-                                                     dev->max_transfer_shift);
-               } else {
-                       dev->max_transfer_shift = max_transfer_shift;
-               }
-       }
-
        return 0;
 }
 
@@ -629,8 +627,8 @@ static int nvme_blk_probe(struct udevice *udev)
        struct blk_desc *desc = dev_get_uclass_platdata(udev);
        struct nvme_ns *ns = dev_get_priv(udev);
        u8 flbas;
-       u16 vendor;
        struct nvme_id_ns buf, *id = &buf;
+       struct pci_child_platdata *pplat;
 
        memset(ns, 0, sizeof(*ns));
        ns->dev = ndev;
@@ -649,8 +647,8 @@ static int nvme_blk_probe(struct udevice *udev)
        desc->log2blksz = ns->lba_shift;
        desc->blksz = 1 << ns->lba_shift;
        desc->bdev = udev;
-       dm_pci_read_config16(ndev->pdev, PCI_VENDOR_ID, &vendor);
-       sprintf(desc->vendor, "0x%.4x", vendor);
+       pplat = dev_get_parent_platdata(udev->parent);
+       sprintf(desc->vendor, "0x%.4x", pplat->vendor);
        memcpy(desc->product, ndev->serial, sizeof(ndev->serial));
        memcpy(desc->revision, ndev->firmware_rev, sizeof(ndev->firmware_rev));
        part_init(desc);
@@ -700,7 +698,7 @@ static ulong nvme_blk_read(struct udevice *udev, lbaint_t blknr,
                c.rw.length = cpu_to_le16(lbas - 1);
                c.rw.prp1 = cpu_to_le64((ulong)buffer);
                c.rw.prp2 = cpu_to_le64(prp2);
-               status = nvme_submit_sync_cmd(dev->queues[1],
+               status = nvme_submit_sync_cmd(dev->queues[NVME_IO_Q],
                                &c, NULL, IO_TIMEOUT);
                if (status)
                        break;
@@ -753,7 +751,7 @@ static ulong nvme_blk_write(struct udevice *udev, lbaint_t blknr,
                c.rw.length = cpu_to_le16(lbas - 1);
                c.rw.prp1 = cpu_to_le64((ulong)buffer);
                c.rw.prp2 = cpu_to_le64(prp2);
-               status = nvme_submit_sync_cmd(dev->queues[1],
+               status = nvme_submit_sync_cmd(dev->queues[NVME_IO_Q],
                                &c, NULL, IO_TIMEOUT);
                if (status)
                        break;
@@ -789,9 +787,7 @@ static int nvme_probe(struct udevice *udev)
 {
        int ret;
        struct nvme_dev *ndev = dev_get_priv(udev);
-       u64 cap;
 
-       ndev->pdev = pci_get_controller(udev);
        ndev->instance = trailing_strtol(udev->name);
 
        INIT_LIST_HEAD(&ndev->namespaces);
@@ -803,13 +799,14 @@ static int nvme_probe(struct udevice *udev)
                goto free_nvme;
        }
 
-       ndev->queues = malloc(2 * sizeof(struct nvme_queue));
+       ndev->queues = malloc(NVME_Q_NUM * sizeof(struct nvme_queue *));
        if (!ndev->queues) {
                ret = -ENOMEM;
                printf("Error: %s: Out of memory!\n", udev->name);
                goto free_nvme;
        }
-       memset(ndev->queues, 0, sizeof(2 * sizeof(struct nvme_queue)));
+       memset(ndev->queues, 0,
+              sizeof(NVME_Q_NUM * sizeof(struct nvme_queue *)));
 
        ndev->prp_pool = malloc(MAX_PRP_POOL);
        if (!ndev->prp_pool) {
@@ -819,9 +816,9 @@ static int nvme_probe(struct udevice *udev)
        }
        ndev->prp_entry_num = MAX_PRP_POOL >> 3;
 
-       cap = nvme_readq(&ndev->bar->cap);
-       ndev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
-       ndev->db_stride = 1 << NVME_CAP_STRIDE(cap);
+       ndev->cap = nvme_readq(&ndev->bar->cap);
+       ndev->q_depth = min_t(int, NVME_CAP_MQES(ndev->cap) + 1, NVME_Q_DEPTH);
+       ndev->db_stride = 1 << NVME_CAP_STRIDE(ndev->cap);
        ndev->dbs = ((void __iomem *)ndev->bar) + 4096;
 
        ret = nvme_configure_admin_queue(ndev);