fsl_pci_init do not scan bus when configured as an end-point

[u-boot] / drivers / pci / fsl_pci_init.c

diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 1e778844a5aad779ae51411ef436139c5fd9d843..38a16e536196c74e3c81162ec878e5193b4cba65 100644 (file)
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -18,8 +18,6 @@
 
 #include <common.h>
 
-#ifdef CONFIG_FSL_PCI_INIT
-
 /*
  * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
  *
@@ -59,8 +57,8 @@ fsl_pci_init(struct pci_controller *hose)
        pci_dev_t dev = PCI_BDF(busno,0,0);
 
        /* Initialize ATMU registers based on hose regions and flags */
-       volatile pot_t *po=&pci->pot[1];        /* skip 0 */
-       volatile pit_t *pi=&pci->pit[0];        /* ranges from: 3 to 1 */
+       volatile pot_t *po = &pci->pot[1];      /* skip 0 */
+       volatile pit_t *pi = &pci->pit[0];      /* ranges from: 3 to 1 */
 
 #ifdef DEBUG
        int neg_link_w;
@@ -112,6 +110,29 @@ fsl_pci_init(struct pci_controller *hose)
                pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
                enabled = ltssm >= PCI_LTSSM_L0;
 
+#ifdef CONFIG_FSL_PCIE_RESET
+               if (ltssm == 1) {
+                       int i;
+                       debug("....PCIe link error. "
+                             "LTSSM=0x%02x.", ltssm);
+                       pci->pdb_stat |= 0x08000000; /* assert PCIe reset */
+                       temp32 = pci->pdb_stat;
+                       udelay(100);
+                       debug("  Asserting PCIe reset @%x = %x\n",
+                             &pci->pdb_stat, pci->pdb_stat);
+                       pci->pdb_stat &= ~0x08000000; /* clear reset */
+                       asm("sync;isync");
+                       for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
+                               pci_hose_read_config_word(hose, dev, PCI_LTSSM,
+                                                       &ltssm);
+                               udelay(1000);
+                               debug("....PCIe link error. "
+                                     "LTSSM=0x%02x.\n", ltssm);
+                       }
+                       enabled = ltssm >= PCI_LTSSM_L0;
+               }
+#endif
+
                if (!enabled) {
                        debug("....PCIE link error.  Skipping scan."
                              "LTSSM=0x%02x\n", ltssm);
@@ -147,8 +168,21 @@ fsl_pci_init(struct pci_controller *hose)
        }
 
 #ifndef CONFIG_PCI_NOSCAN
-       printf ("               Scanning PCI bus %02x\n", hose->current_busno);
-       hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno);
+       pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8);
+
+       /* Programming Interface (PCI_CLASS_PROG)
+        * 0 == pci host or pcie root-complex,
+        * 1 == pci agent or pcie end-point
+        */
+       if (!temp8) {
+               printf("               Scanning PCI bus %02x\n",
+                       hose->current_busno);
+               hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
+       } else {
+               debug("               Not scanning PCI bus %02x. PI=%x\n",
+                       hose->current_busno, temp8);
+               hose->last_busno = hose->current_busno;
+       }
 
        if ( bridge ) { /* update limit regs and subordinate busno */
                pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
@@ -159,7 +193,8 @@ fsl_pci_init(struct pci_controller *hose)
 
        /* Clear all error indications */
 
-       pci->pme_msg_det = 0xffffffff;
+       if (bridge)
+               pci->pme_msg_det = 0xffffffff;
        pci->pedr = 0xffffffff;
 
        pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
@@ -173,5 +208,3 @@ fsl_pci_init(struct pci_controller *hose)
                pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
        }
 }
-
-#endif /* CONFIG_FSL_PCI */