Merge branch 'next' of git://git.denx.de/u-boot-mpc83xx

[u-boot] / drivers / pci / fsl_pci_init.c

diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index e8eb9d6db77c6dbb734aa4861ebdfa847abf4b7c..d55db1a0b691a3243d84f7e817ee69771a1df36d 100644 (file)
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -1,20 +1,7 @@
 /*
  * Copyright 2007-2012 Freescale Semiconductor, Inc.
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -41,12 +28,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #include <asm/io.h>
 #include <asm/fsl_pci.h>
 
-/* Freescale-specific PCI config registers */
-#define FSL_PCI_PBFR           0x44
-#define FSL_PCIE_CAP_ID                0x4c
-#define FSL_PCIE_CFG_RDY       0x4b0
-#define FSL_PROG_IF_AGENT      0x1
-
 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
 #define CONFIG_SYS_PCI_MEMORY_BUS 0
 #endif
@@ -211,7 +192,7 @@ static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
        return 1;
 }
 
-#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 static void fsl_pcie_boot_master(pit_t *pi)
 {
        /* configure inbound window for slave's u-boot image */
@@ -388,7 +369,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
        /* see if we are a PCIe or PCI controller */
        pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
 
-#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
        /* boot from PCIE --master */
        char *s = getenv("bootmaster");
        char pcie[6];
@@ -437,6 +418,15 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
        udelay(1);
 #endif
        if (pcie_cap == PCI_CAP_ID_EXP) {
+               if (block_rev >= PEX_IP_BLK_REV_3_0) {
+#define PEX_CSR0_LTSSM_MASK    0xFC
+#define PEX_CSR0_LTSSM_SHIFT   2
+                       ltssm = (in_be32(&pci->pex_csr0)
+                               & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
+                       enabled = (ltssm == 0x11) ? 1 : 0;
+               } else {
+               /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm); */
+               /* enabled = ltssm >= PCI_LTSSM_L0; */
                pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
                enabled = ltssm >= PCI_LTSSM_L0;
 
@@ -469,7 +459,30 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
                                        PCI_BASE_ADDRESS_0, pcicsrbar);
                }
 #endif
+       }
 
+#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
+               if (enabled == 0) {
+                       serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+                       temp32 = in_be32(&srds_regs->srdspccr0);
+
+                       if ((temp32 >> 28) == 3) {
+                               int i;
+
+                               out_be32(&srds_regs->srdspccr0, 2 << 28);
+                               setbits_be32(&pci->pdb_stat, 0x08000000);
+                               in_be32(&pci->pdb_stat);
+                               udelay(100);
+                               clrbits_be32(&pci->pdb_stat, 0x08000000);
+                               asm("sync;isync");
+                               for (i=0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
+                                       pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
+                                       udelay(1000);
+                               }
+                               enabled = ltssm >= PCI_LTSSM_L0;
+                       }
+               }
+#endif
                if (!enabled) {
                        /* Let the user know there's no PCIe link */
                        printf("no link, regs @ 0x%lx\n", pci_info->regs);
@@ -555,6 +568,10 @@ int fsl_is_pci_agent(struct pci_controller *hose)
                u8 prog_if;
 
                pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
+               /* Programming Interface (PCI_CLASS_PROG)
+                * 0 == pci host or pcie root-complex,
+                * 1 == pci agent or pcie end-point
+                */
                return (prog_if == FSL_PROG_IF_AGENT);
        }
 }
@@ -602,7 +619,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
        if (fsl_is_pci_agent(hose)) {
                fsl_pci_config_unlock(hose);
                hose->last_busno = hose->first_busno;
-#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
        } else {
                /* boot from PCIE --master releases slave's core 0 */
                char *s = getenv("bootmaster");